5.4.1.1 Test FET Layout

A typical common source layout of a 6 finger by 50 μm (6 × 50) test FET structure for modeling and extraction is shown in Figure 5.8. The test structure contains more than just the FET. It contains ground-signal-ground pads (at the extreme left and right) for on-wafer probing and carefully designed nearly 50 Ω transmission lines (the narrow structures attached to the signal pads) to achieve single-mode EM wave propagation for the microwave signals to the device.

Figure 5.8 Test FET pattern for model extraction of a common-source FET.

The S-parameter (and DC) measurements at the probe tips represent the characteristics of the entire structure. In an actual circuit, say a MMIC, the pads and transmission lines are not present. It is therefore essential to characterize and model just the device at the well-defined reference planes where the component is defined, so that the model representing the device can be placed into a circuit for design purposes.

5.4.1.2 Calibration

Calibration, for RF and microwave network analysis measurements, is a very important topic, but will only be summarized briefly here. More details can be found in [3–5]. Poorly calibrated measurements lead to poor models. On-wafer calibration standards are usually best [4], and we will restrict ourselves to this approach.

We need well-calibrated S-parameters at the on-wafer calibration planes of Figure 5.8. The best way to do this is to define on-wafer calibration standards that can be used to move the reference planes from the probe tips to these planes. Four calibration patterns, defining known short, open, load, and thru (SOLT) standards, for RF and microwave calibrations, are shown in Figure 5.9.

Figure 5.9 On-wafer patterns used to help characterize the FET device embedded in the layout of Figure 5.8.

The pads and transmission lines are identical to those of the FET test pattern of Figure 5.8. The first three standards are placed at the calibration planes the same distance apart as in the test FET structure. Only the “zero-delay” thru pattern is different for relative probe placement – the ports are physically closer together so the calibrations planes coincide – since this is a precise way to generate a good thru standard.

The S-parameters from the four patterns of Figure 5.9 are measured, and used together with the measured S-parameters of the test FET layout of Figure 5.8, to determine the S-parameters at the device reference planes. Algorithms are built into modern VNA software that use these four SOLT standards and the test structure measurements to return the S-parameters at the device planes. Alternative sets of on-wafer calibration patterns can be used with different calibration algorithms (e.g., LRRM or multiline TRL methods) to accomplish the same objectives [4].

5.4.1.3 Gate and Drain Manifolds

Before we can move the reference planes to the desired gate and drain boundaries indicated by the dotted lines in Figure 5.8, we must account for the behavior of the port manifolds.

The manifolds are the feed structures between the solid and dotted lines that couple the signals from the ends of the transmission lines of the test structure to the multiple gates and drain bars of the transistor. These structures are implemented very differently when a FET is physically realized as part of a MMIC design, for example. The idea is to model the manifolds of the test structure to move the reference planes and define the device at the dotted lines. The model we will ultimately build and extract, in this and the next chapter, will be for this device between the dotted lines of Figure 5.8. It will be incumbent on the MMIC designer to account for any parasitic effects introduced by the design-specific coupling of this device to others in the circuit, including the multiple gate and drain connections.

The gate manifold, in the layout of Figure 5.8, has source metal crossing over gate metal, with an interlayer dielectric in between. This could be modeled as a set of parasitic capacitors for each crossover and additional capacitors for fringing fields and the vertical bar of metal just to the right of the left solid line of Figure 5.8. A preferred modern approach, however, is to represent the manifold behavior by S-parameters computed directly from the layout using electromagnetic simulations. It is usually sufficient to simulate a 2-port S-parameter matrix with an input port at the calibration plane and an output port corresponding to an effective single gate finger at the inner (device) plane.² A similar simulation from layout can be done for the drain manifold.

With each manifold characterized in terms of its respective two-port S-parameters, simple linear de-embedding methods are used to move the reference planes to the desired device planes – the inner dotted lines in Figure 5.8.

5.5.2.1 Using Bias Conditions to Simplify the Equivalent Circuit for Parasitic Element Extraction from Measurements

Due to the significant dependence on bias of the intrinsic ECPs, the topology of the intrinsic device can be simplified in specific “cold FET” conditions, where the transistor is not active. The total topology of the device model in Figure 5.10 then becomes more amenable to unambiguous extraction, where the parasitic elements can be more readily separated from the intrinsic elements. Under these conditions, the parasitic elements in the different shells of Figure 5.10 can be identified much more easily.

5.5.2.2 Identification of the Parasitic Capacitances

We consider one of the cold FET conditions where V_DSDC = 0VDSDC=0 and the device is reverse-biased to the point where the gate-source voltage is less than the threshold voltage, VGSDC<VT. Under these conditions, where the device is not active, the device intrinsic transconductance, G_mGm must vanish. Under this strong reverse bias condition, we can also assume the intrinsic drain-source resistance, R_DSRDS, is large enough to be neglected, which removes both of those branches from the equivalent circuit of the intrinsic device. If we further limit the characterization frequency range for the S-parameters to be far below the cutoff frequency of the device, we can also usually neglect the series inductances, and since we are ultimately interested in the imaginary part of the admittance elements in the outer shell, we can neglect the series resistances as well. The inductances and resistances will be dealt with by considering a different bias condition in Section 5.5.2.4. This assumes the value of intrinsic C_DSCDS is zero at this particular bias condition.

We are left, therefore, with the combination of outer-shell parasitic capacitances in parallel with the intrinsic device junction capacitances at this reversed bias condition. This simple approximate equivalent circuit topology is shown in Figure 5.11.

Figure 5.11 Simplified parasitic capacitance model of a FET under passive bias condition for parasitic capacitance identification.

Given the topology of the Figure 5.11, the correspondence between the 2-port linear data and the desired ECPs is most easily formulated in the admittance representation. We use the standard formula to convert the S-parameters to the Y-parameters given by (5.3), which follows from (3.36).

Y=1Z0I−S⋅I+S−1(5.3)

The following simple relationships defining the element values in Figure 5.11 in terms of the common source Y-parameters are given in equations (5.4).

CGSx+CGSi=ImY11+Y12ωCGDx+CGDi=−ImY12ωCDSx=ImY22+Y12ω(5.4)

Here C_GSi and C_GDiCGSiandCGDi are the intrinsic capacitances of the junction at the particular cold bias point, and C_GSx, C_GDx, and C_DSxCGSx,CGDx,andCDSx are the parasitic values that, being assumed independent of bias, are to be identified.

There are still too many unknown parameters (five) on the left side of equations (5.4), to identify them all from one set of device admittances. Therefore, we characterize an array of devices of physically scaled layouts, shown in Figure 5.12, of various numbers of parallel gate fingers with various finger widths, and use the resulting geometrically dependent ECP values to separate parasitic from intrinsic element values.

Figure 5.12 FET array of scaled layouts to identify parasitic elements.

Fitting the first equation of (5.4), from data for each set of devices with the same number of fingers separately, we get the plots of Figure 5.13 where the intercepts (extrapolation to zero width) provide the values for the parasitic capacitances of devices with different numbers of fingers. This interpretation assumes that the intrinsic capacitance values, extrapolated to zero gate width are zero. This is a physically reasonable approximation neglecting only fringing fields and perimeter effects that are usually insignificant for practical FET geometries.

Figure 5.13 Linear regression allows for parasitic capacitance identification.

It is a good sanity check that the slopes of the three independently fitted lines plotted in Figure 5.13, are so consistent.

Plotting the values of C_GSxCGSx versus the number of fingers, we obtain the geometrical scaling rule from the linear fit shown in Figure 5.14.

Figure 5.14 Scaling rule for shunt parasitic gate-source capacitance versus finger number.

A similar approach can be taken for the remaining parasitic elements in Figure 5.11.

5.5.2.3 Stripping Off the Outer Admittance Shell

With the parasitic capacitance values of the outer parasitic shell now known, the two-port description at the device plane can be moved to the plane of the parasitic impedances.

Given the topological representation of these parasitics, the relationship between the common source two-port parameters at the Y and Z planes can be expressed most simply according to (5.5). The subtraction is element by element in the admittance representation, and it gives the common-source Y-parameters with the parasitic capacitances removed (Figure 5.15). The inverse of this difference is, therefore, the Z-parameter matrix, Z, at the plane of the series parasitics.

Z−1=Y−Ypara=Y−jωCGSx+CGDx−CGDx−CGDxCGDx+CDSx(5.5)

In (5.5), we have computed the common source parasitic admittance matrix, Y^paraYpara, in terms of the parasitic capacitance elements using the definition of the admittance matrix according to (5.6) and the structure of Figure 5.2.

Yij≡δIiδVjδVk≠j=0(5.6)

Figure 5.15 Structure after stripping parasitic capacitances using equation (5.5).

5.5.2.4 Parasitic Resistance and Inductance Extraction

We now move on to extracting the series parasitic shell containing the resistances and inductances. The strategy is similar to the capacitance parasitic extraction step of 5.5.2.2, in that we choose a bias condition to simplify the equivalent circuit, but this time the operating conditions are quite different. We will also do a matrix subtraction to remove the parasitic elements, but this time, due to the topology, we do so in the impedance domain.

Direct Method Based on Extreme Forward Bias Condition

A significantly forward-biased gate voltage is chosen such that there is substantial current flowing into the gate terminal across the Schottky barrier. The drain-source voltage is chosen to be zero, or, nearly equivalently, the drain current is biased to be equal and opposite to half the gate current. That is, IDDC=−IGDC2. This condition forces the drain and source current to be equal.

This DC condition is assumed to be sufficiently extreme so as to effectively short out the Schottky barrier junction, interpreted as a strongly forward biased diode with, therefore, a very large conductance. The large conductance presents an effective electrical short between this intrinsic gate node and any other node to which it is connected in the intrinsic equivalent circuit. That is, the entire intrinsic FET can be collapsed to a single node, reducing the equivalent circuit topology within the Z-shell to a simple T-topology shown in Figure 5.16.

Figure 5.16 Idealized highly forward-biased FET equivalent circuit after the capacitance shell is stripped off. The intrinsic FET is assumed to be shorted out.

We remind the reader that gate current was not explicitly accounted for in the simple equivalent circuit of Figure 5.2. We assume a large conductance only at this stage in order to identify the series parasitic elements. The final linear model will be valid only for conditions where the actual gate leakage is negligible.

From Figure 5.16, we note only six equivalent circuit elements, all series parasitic elements, remain in the total model topology, now that the parasitic capacitances have been stripped off and the intrinsic device collapsed to a point at this bias condition. These EPCs can therefore be directly identified from the real and imaginary parts of the Z-matrix of the data at this plane. This follows from the computation of the parasitic Z-matrix, given in (5.7) in common source configuration, which follows from the definition (5.8), applied to the circuit representation of Figure 5.16.

Zpara=RG+RSRSRSRD+RS+jωLG+LSLSLSLD+LS(5.7)

Zijpara≡δViδIjδIk≠j=0(5.8)

While formally (5.7) can be solved for the six ECPs at any frequency by taking simple linear combinations of the real and imaginary parts of the Z-matrix, the frequency of the measurements must be high enough to measure the inductances without too much uncertainty. A fit to (5.7) from data over a range of moderate-to-high frequencies generally provides a more robust extraction than a direct solution from data at a single CW frequency.

This method has the following drawbacks, however. The extreme forward bias condition may be too stressful for modern short gate-length devices, causing damage during the measurements. Since R_D and R_S, are physically semiconductor access resistances, and as such can be current dependent, their extraction from data at an extreme bias condition may yield parameter values that might be different from their actual values under more normal operating conditions.

Modified Procedure at Less Extreme Forward Bias

A method that is potentially more accurate, but also more complicated, than that of 5.5.2.4.1, is presented in reference works [8–10]. In this case, the gate bias is only slightly forward biased, just enough to get the channel as open as possible but at much less extreme forward current conditions through the gate than 5.5.2.4.1. The intrinsic device is therefore not completely shorted out and an approximate modeling of its composition is required. The equivalent circuit of the series parasitics and the intrinsic device at this bias condition is shown in Figure 5.17 [1,10].

Figure 5.17 Forward bias FET equivalent circuit at V_DS = 0 V and V_GS = 0.3 V for parasitic resistance and inductance extraction.

The parameters R₁ and C₁R1andC1 are associated with the total gate intrinsic resistance and capacitance, respectively, and R_chRch represents the active channel resistance at this bias condition. The fractional factors of R_chRch come from an analysis of the device as a distributed structure [11,12]. In this three-terminal schematic, the contribution of the seemingly strange −Rch6 factor at the gate with the Rch2 factors at the drain and source are equivalent to the more familiar common-source Z-parameters reported in the literature. The value of R_chRch has to be estimated from data on other test structures, and its value depends on the material properties of the semiconductor. The authors use 1.55e-4 ohm-meter for GaAs and 6.75e-4 ohm-meter for GaN. Values of R₁ and C₁R1andC1, along with the other six parameters in the impedance shell, are then optimized to fit the measured Z-parameters over a wide frequency range. More detailed considerations can be found in [1].

By applying either the methodology of Section 5.5.2.4.1 or that of 5.5.2.4.2, or equivalent, over the FET array of sizes, one can extract the values and the geometrical scaling rules for the parasitic elements. The data from an array of layouts and the resulting scaling rule for the drain resistance, R_D, of a GaAs FET is given in Figure 5.18.

Figure 5.18 Dependence of the parasitic drain resistance as a function of total gate width, as fitted to data from devices of multiple layouts.

Similar results are found for the source resistance.

A similar analysis leads to the gate resistance, R_G, but its scaling rule is quite different.

5.5.2.5 Gate Resistance Scaling

Geometrical Argument

From an examination of the common-source layout of Figure 5.3, given that the gate current flows along the fingers from left to right, we would expect, from simple geometrical arguments, the gate resistance to increase roughly linearly with the width per finger, w, for a fixed number, N, of parallel gate fingers.³ For the same value of w, the resistance should scale inversely with N, because the fingers are arranged in parallel. The total gate width, W^tot, is just the product of the width per finger and the number of fingers, so we have W^tot = N ⋅ wWtot=N⋅w. From these considerations we derive a simple gate resistance scaling rule according to (5.9) with parameters α≈1α≈1 and β≈2β≈2. Here the ref superscript refers to the values of a particular reference device. Note how different the rule for gate resistance scaling is compared to that of the source and drain resistance, the latter given by a simple expression such as shown in Figure 5.18. The rule (5.9) enables the estimation of the gate resistance for a range of geometries specified in terms of total gate width, W^tot, and number of parallel gate fingers, N. This can be simply re-expressed in terms of the width-per-finger, w, if desired (see Exercise 5.7). Obviously, care must be used to properly interpret the meaning of the geometrical parameters that define the device.

RG=RGref⋅WtotWtot_refα⋅NrefNβ(5.9)

Empirical Results

Alternatively, an approach similar to that of 5.5.2.4 for the drain and source resistances can be followed for the gate resistance to arrive at an empirical expression for the gate resistance, R_G, as a function of the total gate width and the number of parallel gate fingers. The results are shown for a pHEMT process in Figure 5.19. While the scaled R_G values move in the same direction with W^tot and N as predicted by (5.9) for positive exponent values, the actual best fit values for the exponents are different. The data and parameter values are shown in Figure 5.19.

Figure 5.19 Empirical scaling rule for gate resistance of a GaAs pHEMT process. Measured (symbols) and best fit to formula (lines) with α = 0.23, β = 1α=0.23,β=1. An ideal lumped physical model predicts α = 1, β = 2.α=1,β=2.

5.6.3.1 Problems Caused by Poor Parasitic Element Extraction

The following example illustrates what happens when there is a poor extraction of the parasitic element values. Broadband S-parameters are measured at a particular active bias condition for a GaN HFET. The device is a 0.15 μm × 6 finger × 60 μm GaN HFET with individual source vias from Raytheon Integrated Defense Systems [13]. The device is optimized for 1–40 GHz operation for applications including power amplifiers, low noise amplifiers, and switch applications. All further examples of GaN transistors in this chapter are based on this device.

The parasitic shells are stripped away using the methods of 5.5.2.4. The resulting intrinsic elements are computed, at each frequency, using the formulas (5.12)–(5.16). The resulting element values versus frequency are plotted for selected elements for two different values of the parasitic source inductance, L_G in Figure 5.23.

Figure 5.23 Flatness with frequency of intrinsic ECPs of a GaN HFET device for two values of parasitic inductance, L_G. The bias condition is V_GS = −1.8 V and V_DS = 20 V. The device is a 0.15 μm × 6 finger × 60 μm GaN HFET with individual source vias from Raytheon Integrated Defense Systems [13]. The device is optimized for 1–40 GHz operation for applications including power amplifiers, low noise amplifiers, and switch applications.

The frequency dependence of the intrinsic elements is much flatter over the wide range of the measurements with the (correct) smaller value of L_GLG. While this example may strike the reader as somewhat extreme, the gate inductance can be difficult to obtain without a large uncertainty. However, it evidently has a significant effect on the frequency flatness of the computed intrinsic elements. Flatness with frequency can be used as an optimization objective in more sophisticated (but more complicated) approaches to the total extraction problem. See for example [14].

With the correct values of the parasitic elements determined, the intrinsic ECPs of the model at each operating point can be determined from the small-signal intrinsic Y-parameters using (5.12)–(5.16) at a single frequency, provided the frequency is not so low that there is large uncertainty in elements, such as capacitances. Examining the capacitance values in Figure 5.23, we see large fluctuations in values below 5 GHz, indicating we should choose a higher frequency for the extraction point. Beyond about 30 GHz we observe an increasing spread in the values versus frequency. So in this case, we choose 10 GHz to be the extraction frequency.

The proof that the model topology and the parameter extraction methodology described here produce accurate linear models is shown in Figures 5.24 and 5.25. In these figures, the broadband measured S-parameters on the 6 × 60 μm GaN HFET are compared with the linear model simulations at two different bias conditions. The fit is quite good over the full range from 0.5 GHz to 50 GHz for both bias conditions, even though the identification of the ECPs for the intrinsic model were identified at only the single CW frequency of 10 GHz. There is a slight discrepancy visible between the measurements and simulations for mid-frequency S₁₁ and S₂₂ and the mid-to-high-frequency gain, S₂₁, is slightly underestimated by the model. A more advanced model will be presented in Section 5.6.4 that improves upon these results.

Figure 5.24 Broadband validation of the linear model of the 6 × 60 μm GaN HFET. Measured (symbols), modeled (lines). Frequency range is 0.5–50 GHz. DC bias conditions: V_GS = −1.8 V, V_DS = 20 V. The model ECPs were identified at 10 GHz.

Figure 5.25 Broadband validation of the linear model of the 6 × 60 μm GaN HFET. Measured (symbols), modeled (lines). Frequency range is 0.5–50 GHz. DC bias conditions: V_GS = −1.2 V, V_DS = 6 V. The model ECPs were identified at 10 GHz.

An important implication of (5.12)–(5.16) is that the identification of the element values can be done at any single CW measurement frequency. This is the principle of “direct extraction” that has become standard industry practice since the late 1980s [6,7]. That is, once it is established that (5.16) is essentially independent of frequency, the particular fixed value of the ECPs can be obtained by a spot measurement at a single CW frequency.

Of course, in practice the extraction frequency must be high enough for the S-parameters at the calibration plane to register a capacitance contribution, but not so high that the data at the intrinsic transistor becomes overly sensitive to additional distributed effects or errors in the parasitic element value extraction (such as the port inductances).

In principle, for a given bias condition, there is an optimum value of frequency for identifying the element values from (5.12) to (5.16). Detailed considerations including uncertainty analysis are presented in [15,16].

The model of Figure 5.20 effectively compresses the independent measurement data from a great many frequencies, into only five real numbers, specifically the values of G_m, G_DS, C_GS, C_GD, and C_DS. These five numbers are predictive of the broadband frequency performance of the intrinsic device through the model. Even including the parasitic elements, the complete linear model is an extremely compact representation of the DUT frequency behavior at the given DC bias point.

Another consequence of the predictive power of the model is that the model can be used to extrapolate beyond the measurement data used to identify the element values. We can identify the element values using (5.12)–(5.16) at any one frequency, say 10 GHz, (or over a moderate range of frequencies, say 5–20 GHz) and then simulate with the model at a CW frequency of, say, 50 GHz. Recall the model frequency performance is determined completely from the element values and their arrangement in the circuit topology. So a well-extracted model will work well until the simulation frequency is so high the device topology is no longer valid. Predictions of DUT performance up to a large fraction of the transistor cutoff frequency, f_T, are reliable if the model parameter extraction has been done properly. Moreover, such simulations can be more accurate than an actual measurement at the desired high frequency. Of course this depends on the instrument measurement bandwidth and the quality of the test transistor layout and calibration patterns. Nevertheless, transistor figures of merit (FOM) such as f_T and f_max, can often be obtained more reliably and much less expensively by first extracting, from high-quality medium frequency data, a model of the device and then simulating with the model at frequencies higher than those used for the extraction to compute the FOM. In fact, this is often the way these device FOMs are defined.

5.6.4.1 Discussion

The use of a transcapacitance element brings with it some complications, however, one of which will be described now. The magnitude of the transadmittance, (5.18), of the intrinsic model increases without bounds as the stimulus frequency increases due to the transcapacitance element. This follows from the small-signal relationship (5.19), deduced from (5.18) by calculating the magnitude of the drain current response to a perturbation in the gate-source voltage. The parameter ττ is defined as the ratio of the magnitude of the transcapacitance to the transconductance. Fortunately, the terminal resistances R_G and R_S, in conjunction with the intrinsic gate capacitances, produce an input time constant that provides a frequency limit beyond which the intrinsic transadmittance won’t increase. The overall model is, therefore, generally quite accurate up to a significant fraction of the transistor cutoff frequency. Nevertheless, the high-frequency behavior of (5.19), even for an intrinsic control frequency limited by input charging time constants, may not follow the measured and physically required decrease with frequency of the transadmittance at extremely high frequencies.

δI2=Gm2+ω2Cm2⋅δV1=GmδV1⋅1+ωτ2τ≡CmGm(5.19)

At the DC bias point V_GS = −1.8 V, V_DS = 20 V, the model parameter values are C_m =  − 110 fFCm=−110fF and G_m = 0.075 SGm=0.075S, so τ = 1.5 psτ=1.5ps. Even at 50 GHz, ωτ = 0.47ωτ=0.47, and the square root factor is only 1.1, so things still work well.

For linear models, there is a classical approach that associates a time-delay with the transconductance element that can account for the measureable behavior shown in Figure 5.26 without the need for a transcapacitance element. This will be described in Section 5.6.5.1. The time-delay approach is not as easily generalized to the large-signal case as the transcapacitance approach, however. We will return to the transcapacitance issues in Chapter 6 when we discuss the large-signal model.

5.6.5.1 Model with Time-Delay of the Transconductance

Historically, another parameter had long been introduced to deal with the imaginary part of the nonreciprocity of the off-diagonal intrinsic admittance parameters for linear models. The most common approach is a time-delay associated with the transconductance element. The frequency-domain representation of a time-delay is a complex number on the unit circle with a phase proportional to the frequency, where the delay parameter, ττ, is the coefficient of proportionality. The ττ parameter varies with the DC bias just like the other intrinsic ECPs. The circuit diagram, with this term added, is shown in Figure 5.31 with the corresponding admittance matrix representation in (5.20).

YCS=00Gme−jωτGDS+jωCGS+CGD−CGD−CGDCGD+CDS(5.20)

The new model parameter is now the time-delay, τ. The relationship between (5.18) and (5.20) can be understood by expanding the exponential of (5.20) in orders of ωτ.

Gme−jωτ≈Gm−jωGmτ+…=Gm1−jωτ+Oωτ2Cm=−Gmτ(5.21)

So the transcapacitance of (5.18) can be interpreted as a first order approximation to the delay of the transcondctance. Alternatively, the C_m value can be identified from data using the formula of (5.17) and used to solve for the parameter τ in (5.20) using the second equation of (5.21).

Figure 5.31 Variant of the intrinsic linear equivalent circuit model for a FET.

As discussed in Section 5.6.4.1, this is still a good approximation even at 50 GHz. Given the improved results using the transcapacitance demonstrated in Figures 5.29 and 5.30, it is clear the model is quite improved over this frequency range.

5.6.5.2 Adding R_GS and R_GD Elements

The intrinsic models of Figures 5.27 and 5.31 have six elements, each of which can be determined from a simple closed-form expression involving the intrinsic Y-parameters from data at any CW frequency. Since there are 8 (real) parameters in the 2×2 intrinsic Y-parameters, we might well ask if there are another two circuit elements that can be identified from the remaining 2 real parameters that could further improve the model. The answer is generally yes. Contrary to what is predicted by (5.18) and (5.20), the measured real parts of Y₁₁ and Y₁₂ are not exactly zero, and the measured imaginary parts are not exactly proportional to frequency. These facts suggest we might be able to add a resistor to each of the gate-source and gate-drain branches to improve the model agreement with the measurements.

From any single frequency measurement, it would not be possible to decide whether these new resistors should be placed in series with the input capacitances or in parallel. Over a broad frequency range, however, for bias conditions for which there is negligible gate leakage, the series combination fits the frequency-dependent data much better. The corresponding model appears in Figure 5.32. This choice can be seen as a natural consequence of good data analysis. There is also a physically based interpretation for these resistors, namely that the displacement current through the gate must go through some of the resistive semiconductor channel before appearing at either intrinsic source or drain terminal.

Figure 5.32 Eight-element intrinsic linear FET model.

The two new elements require a modification of the formulas expressing the eight ECPs as explicit linear combinations of the intrinsic Y-parameters. We do this in a two-step process. We define the following linear combinations of common-source Y-parameters shown in (5.22). The expressions for each element, shown in (5.23), follow from simple algebra [6].

YGD=−Y12YGS=Y11+Y12YDS=Y12+Y22Ym=Y21−Y12(5.22)

RGS=Re1YGSRGD=Re1YGDCGS=−1ImωYGSCGD=−1ImωYGDGDS=1RDS=ReYDSCDS=ImYDSωGm=ReYmCm=ImYmω(5.23)

The expressions for C_GS and C_GDCGSandCGD in (5.23) reduce to those of (5.15) and (5.14), respectively, in the low-frequency limit. However, those of (5.23) are more sensitive to noisy data or if the data is affected by DC leakage at the measurement condition.

For some active bias conditions, the actual values of C_GD are so small that to accurately resolve the R_GD element in series with it, a stimulus frequency either beyond the measurement BW of conventional VNAs is required, or else the large uncertainty in the extracted R_GD element value can reduce the usefulness of this model. In such cases, it may be better to put the R_GD element in parallel with C_GD. (keeping R_GS in series with C_GS). In this case, R_GD represents DC gate-drain leakage. While this makes for a model with an asymmetric equivalent circuit topology, we must remember that the active bias condition itself “breaks the symmetry” of the device structure, so this presents no problem for a linear model where the element values are fixed.

5.7.1.1 Limitations of Simple Geometrical Scaling Rules

The geometrical scaling rules introduced above are only approximate. They hold over a certain range of layouts, or, equivalently, values of the scaling ratio, r. Simple scaling starts to break down at very high frequencies, where device distributed effects become important for large finger widths.⁴

5.7.1.2 DC Bias Conditions Are Not Computed

It is important to understand that the DC input parameters must be supplied by the user and are not related to the DC operating point computed by the simulator (unlike a general large-signal model). So if the transistor of interest is embedded in a circuit with a lossy path from the bias supplies, the designer must estimate the actual terminal voltages the device will see and provide the correct, actual terminal voltage differences for the device through the model instance of Figure 5.34.