### 5.1 Introduction: Linear Equivalent Circuit Models of Transistors

This chapter introduces the major principles and methods of linear device modeling. Specifically, we present an introduction to models of transistors based on linear equivalent circuits. The equivalent circuit description attempts to associate the electrical model description with the physical structure of the device.

The models are linear in the sense we have described in detail in Chapters 1 and 3, specifically that the response of such a model to a superposition of stimuli is equal to the superposition of responses to the stimuli applied independently. As we have learned in Chapter 1, linearity implies that an RF sinusoidal signal applied at a particular frequency will produce a sinusoidal response at (only) the same frequency. We can then completely describe the linear model in terms of any one of several equivalent conventional small-signal frequency-domain descriptions, such as admittance, impedance, or scattering parameters.

Although the response of linear device models is proportional to the complex amplitudes (phasors) of the input stimuli, as with linear behavioral models, the explicit dependence on frequency of the response is *not* linear. That is, the response at frequency *2f* is not twice the response at frequency *f*. Each linear circuit element contributes to the network description an admittance (or impedance, or S-parameter), a complex valued frequency-dependent number that defines the proportionality of complex-valued response to stimulus. Resistors contribute real-valued impedances independent of frequency, while ideal capacitors and inductors contribute admittances and impedances, respectively that are purely imaginary and proportional to frequency. Note that the capacitance, or the inductance, values themselves are independent of frequency. For a model composed exclusively of lumped elements, the model response is a rational function (i.e., it is given by the ratio of two polynomials) of frequency. The quantitative response also depends, of course, upon the numerical values of the elements (e.g., the resistances and capacitances).

This chapter also presents an introduction to parameter extraction. The parameters of the linear equivalent circuit model are the values (e.g., the resistance or capacitance) of each of the corresponding elements of the equivalent circuit. Parameter extraction is the process of determining the numerical values for these parameters, from measured or simulated data. The typical data used for linear RF and microwave device model parameter extraction are S-parameters. This is natural because the measurements are (ideally) linear, like the models. We will see, however, that even for purely linear microwave and RF device models, several distinct DC bias conditions must be applied. This is necessary to put the device in the appropriate operating condition for a useful linear model and to provide distinct states of device operation to help in the extraction of parasitic element values necessary to correctly determine all the device model parameters from data at the externally accessible measurement ports.

The modeling and parameter extraction processes are highly related. The full transistor model is constructed from linear electrical element building blocks (e.g., resistors and capacitors) by putting them together in a particular network – the equivalent circuit topology – in order to represent the overall device behavior. Parameter extraction is, in a rough sense, the reverse process, namely going from information at the device external terminals and using knowledge of the presumed topology to determine the numerical values of the individual electrical circuit parameters (ECPs), (e.g., the capacitance and resistance values of the primitive elements).

For this chapter we stay exclusively in the frequency domain. We will meet linear models again in Chapter 6 where we show how they arise, generally, as first-order approximations to nonlinear models in the small-signal limit. Recall we already met a particularly simple linear FET model derived from time-domain considerations in Chapter 3 (Section 3.12).

### 5.2 Linear Equivalent Circuit of a FET

A simple picture of a Field Effect Transistor (FET) is shown in Figure 5.1.

Figure 5.1 Simple FET structure with equivalent circuit elements superimposed.

Metal electrodes, labelled Source, Gate, and Drain, are shown on the top of the figure, typical of a GaAs pHEMT device (but not drawn to scale). The source and drain electrodes make ohmic contacts with a highly doped layer of semiconductor. The gate metal makes a Schottky contact with a different semiconductor layer. The active semiconductor channel, through which most of the current flows, is represented by the lighter region below. The substrate, taken as semi-insulating, is shown as the bottom layer.

The type of circuit elements and their arrangement in the equivalent circuit are consequences of our physical understanding of the device physics and its structure. The Schottky contact presents a barrier to (DC) current flow, so there is no resistor in the electrical path from the gate terminal to the channel in this simple idealization. The ohmic contacts permit current flow through the semiconductor, so there are resistances in the path from the source and drain terminals. The metal electrodes themselves are represented by inductors that affect the high-frequency RF and microwave signals. The Schottky contact sets up a built-in electric field at the gate metal-semiconductor interface that depletes charge carriers in the semiconductor depending also on the applied bias voltages at the terminals. This is modeled by parallel plate capacitors, labelled *C*_{GS} and *C*_{GD}. The current source element represents the main current flow in the channel and is responsible for the transistor action. Although not clear from the figure, it is electrically controlled by the local potential differences that result from applied bias conditions at the external terminals taking into account the voltage dropped across the resistors. Coupling between drain and source terminals is represented by the *C*_{DS} element.

There also exists capacitive coupling among some of the physical features of the device structure that should be modeled by additional circuit elements to complete the idealized electrical model. A planar schematic that illustrates the model in somewhat more detail is shown in Figure 5.2.

Figure 5.2 Simplified equivalent circuit of a FET with parasitic and intrinsic ECPs.

The model of Figure 5.2 is further divided into the intrinsic model, within the dashed box, with the remaining elements belonging to the extrinsic or parasitic model. The extrinsic part is represented by shells of parasitic shunt capacitance elements, within which is a shell of series-connected resistances and inductances. We will make use of this structure in the parameter extraction process. Various topologies are used [1], some more elaborate, but for simplicity, we will restrict ourselves to this.

The shunt capacitances represent metal-to-metal interelectrode parasitic effects. The resistors *R*_{S} and *R*_{D}, considered parasitic elements in this treatment, represent the “access resistance” – that portion of the semiconductor that is not controlled by the gate potential. The gate resistor, *R*_{G,} is largely attributable to the resistance of the gate metallization. Inductances are also associated with the electrode metal and become important at high frequencies.

The intrinsic transistor is the heart of the semiconductor device. The intrinsic transistor model accounts for the bias-dependent transconductance responsible for the transistor action, channel resistance, and the bias-dependent junction capacitances. Although not visible in the structure of Figure 5.1, the physical mechanisms of self-heating, and in some cases, charge trapping, can be considered part of the intrinsic device. These phenomena are modeled by additional coupled equivalent circuits that will be introduced in Chapter 6.

#### 5.2.1 Bias Considerations

The isolated structure of the transistor shown in Figure 5.1 provides no information about the DC operating condition at which the linear model is defined. Different device operating regimes, specified by different bias conditions, substantially affect the numerical values of the ECPs of the intrinsic model. Implicitly, this means a linear device model is defined for a specific bias condition.

Linearity requires that the ECPs do not vary with the applied RF signal. And, as these ECPs are dependent on the DC biases, these DC biases do not change with the RF signal. The DC conditions merely parameterize the linear dependence of the RF input-output relations. Since physical transistors are nonlinear components, as we learned in Chapter 1, a linear transistor model is a valid approximation to the actual device behavior provided the device is stimulated by a sufficiently small RF signal. This is why linear models of transistors are often referred to as *small-signal* models.

There is no precise way to know, *a priori*, how small such signals need to be for a linear model to be considered valid. Formal procedures for the linearization of the nonlinear equations to produce linear models in the small-signal limit are described in Chapter 6. Recall a particularly simple linear FET model was derived from time-domain considerations in Chapter 3 (Section 3.12), and ultimately converted to an S-parameter representation.

Linear device models are useful primarily to describe the device small-signal behavior in an active bias operating condition.^{1} At such bias conditions, we can usually neglect forward and reverse gate leakage currents, which would require a more complicated equivalent circuit representation for Figure 5.2 with additional elements. However, we will see in Section 5.5.2.1 that deliberately choosing bias conditions outside the range of normal small-signal operation can be useful for parasitic element value extraction, necessary to ultimately get the best model for simulation at the standard conditions.

#### 5.2.2 Temperature Considerations

Temperature, analogously to bias, affects the linear equivalent circuit element values. But just as with bias, for a linear model we can usually take the device temperature to be fixed and independent of the RF signal. As long as the device is operating in the small-signal regime, this assumption is valid for most RF applications. However, as we will see in Chapter 6, there can still be a frequency-dependence to the device small-signal electrical response caused by a *temperature modulation* produced by a small-signal stimulus *if the applied signal is varied slowly enough*. Since timescales for this phenomena are typically of the order of milliseconds or longer, and the RF timescales are typically in the nanosecond range, we neglect this phenomenon in this chapter. We deal with electro-thermal considerations in Chapter 6.

### 5.3 Measurements for Linear Device Modeling

#### 5.3.1 Terminal Mappings to RF Measurement Ports

The device structure and equivalent circuit shown in Figures 5.1 and 5.2 has three external terminals, one each for the gate, drain, and source, respectively. Microwave measurements are made on actual layouts – physical realizations of the transistor embedded or “wired” into a particular two-port structure. The resulting measurement data will usually be in the form of a 2 × 2 matrix, such as a two-port S-parameter or Y-parameter representation. There are several ways a two-port matrix description, and therefore the actual physical structure of the test FET for measurement purposes, can be mapped to and from the three-terminal schematic of Figure 5.2. This depends on the choice of a common terminal and the choice of the numerical ordering of the ports.

Examples of the two most common physical realizations of actual test FET layout structures, and their wiring diagrams mapping the three terminals to distinct two-port configurations, are presented in Figures 5.3–5.6 [2]. These are *common source* and *common gate* layouts, respectively, and typically have the ports ordered as shown. The relationships between the ECP values of the FET equivalent circuit and the data are completely different when the two-port parameters are provided in common source or common gate configuration.

Figure 5.3 Common-source layout of a multifinger FET.

Figure 5.4 Wiring diagram of a three-terminal device consistent with the common-source layout of Figure 5.3. Port one is the gate and port two is the drain.

Figure 5.5 Common-gate layout.

Figure 5.6 Wiring diagram of a three-terminal model corresponding to the common-gate layout of Figure 5.5. Port one is the drain and port two is the source.

To make this point more concrete, imagine, for the moment, that we can neglect the inductances and resistances in the extrinsic equivalent circuit of Figure 5.2. We could then identify each intrinsic ECP from the two-port parameters in either common source or common gate configuration. For example, the formula for the feedback capacitance, *C*_{GD}, in terms of common source Y-parameters is given in (5.1) and the corresponding formula in terms of common-gate Y-parameters is shown in (5.2), where the superscripts are used to label the respective two-port configuration. The formulas (5.1) and (5.2) correspond to the port orderings specified in the diagrams of Figures 5.3–5.6. Other port orderings lead to different but related formulas. In the Appendix we show explicit formulas to relate these descriptions under ideal circumstances.

It is therefore essential for parameter extraction to know the particular two-port realization of the physical device, including the ordering of the ports.

### 5.4 On-Wafer Measurements and Calibration

Transistor S-parameters for modeling purposes are best made on-wafer using vector network analyzers (VNA). A typical test bench is shown in Figure 5.7. A semi-automated wafer probe station is shown with a wafer, micro-manipulators for probing, microwave ground-signal-ground (GSG) probes and a microscope for visualization. A 50 GHz VNA with built-in sources is visible behind the probe station. Bias voltages are controlled and monitored with multiple source monitor units (SMUs) as shown on the left. A temperature controller is also shown that is used to set the temperature of the chuck on which the wafer is placed, providing controllable thermal boundary conditions for the transistor.

Figure 5.7 Test bench for S-parameter measurements for modeling.

#### 5.4.1 Linear Device Modeling Flow

The linear modeling flow is the process of making well-calibrated microwave measurements on one or more FET test patterns and using the information to obtain the ECPs for the corresponding model, sometimes including the geometrical scaling rules for the ECPs in the process.

##### 5.4.1.1 Test FET Layout

A typical common source layout of a 6 finger by 50 μm (6 × 50) test FET structure for modeling and extraction is shown in Figure 5.8. The test structure contains more than just the FET. It contains ground-signal-ground pads (at the extreme left and right) for on-wafer probing and carefully designed nearly 50 Ω transmission lines (the narrow structures attached to the signal pads) to achieve single-mode EM wave propagation for the microwave signals to the device.

Figure 5.8 Test FET pattern for model extraction of a common-source FET.

The S-parameter (and DC) measurements at the probe tips represent the characteristics of the entire structure. In an actual circuit, say a MMIC, the pads and transmission lines are not present. It is therefore essential to characterize and model just the device at the well-defined reference planes where the component is defined, so that the model representing the device can be placed into a circuit for design purposes.

##### 5.4.1.2 Calibration

Calibration, for RF and microwave network analysis measurements, is a very important topic, but will only be summarized briefly here. More details can be found in [3–5]. Poorly calibrated measurements lead to poor models. On-wafer calibration standards are usually best [4], and we will restrict ourselves to this approach.

We need well-calibrated S-parameters at the on-wafer calibration planes of Figure 5.8. The best way to do this is to define on-wafer calibration standards that can be used to move the reference planes from the probe tips to these planes. Four calibration patterns, defining known short, open, load, and thru (SOLT) standards, for RF and microwave calibrations, are shown in Figure 5.9.

Figure 5.9 On-wafer patterns used to help characterize the FET device embedded in the layout of Figure 5.8.

The pads and transmission lines are identical to those of the FET test pattern of Figure 5.8. The first three standards are placed at the calibration planes the same distance apart as in the test FET structure. Only the “zero-delay” thru pattern is different for relative probe placement – the ports are physically closer together so the calibrations planes coincide – since this is a precise way to generate a good thru standard.

The S-parameters from the four patterns of Figure 5.9 are measured, and used together with the measured S-parameters of the test FET layout of Figure 5.8, to determine the S-parameters at the device reference planes. Algorithms are built into modern VNA software that use these four *SOLT* standards and the test structure measurements to return the S-parameters at the device planes. Alternative sets of on-wafer calibration patterns can be used with different calibration algorithms (e.g., LRRM or multiline TRL methods) to accomplish the same objectives [4].

##### 5.4.1.3 Gate and Drain Manifolds

Before we can move the reference planes to the desired gate and drain boundaries indicated by the dotted lines in Figure 5.8, we must account for the behavior of the port manifolds.

The manifolds are the feed structures between the solid and dotted lines that couple the signals from the ends of the transmission lines of the test structure to the multiple gates and drain bars of the transistor. These structures are implemented very differently when a FET is physically realized as part of a MMIC design, for example. The idea is to model the manifolds of the test structure to move the reference planes and define the device at the dotted lines. The model we will ultimately build and extract, in this and the next chapter, will be for this device between the dotted lines of Figure 5.8. It will be incumbent on the MMIC designer to account for any parasitic effects introduced by the design-specific coupling of this device to others in the circuit, including the multiple gate and drain connections.

The gate manifold, in the layout of Figure 5.8, has source metal crossing over gate metal, with an interlayer dielectric in between. This could be modeled as a set of parasitic capacitors for each crossover and additional capacitors for fringing fields and the vertical bar of metal just to the right of the left solid line of Figure 5.8. A preferred modern approach, however, is to represent the manifold behavior by S-parameters computed directly from the layout using electromagnetic simulations. It is usually sufficient to simulate a 2-port S-parameter matrix with an input port at the calibration plane and an output port corresponding to an effective single gate finger at the inner (device) plane.^{2} A similar simulation from layout can be done for the drain manifold.

With each manifold characterized in terms of its respective two-port S-parameters, simple linear de-embedding methods are used to move the reference planes to the desired device planes – the inner dotted lines in Figure 5.8.

### 5.5 The Device

The S-parameter data, now transformed to the device planes, are indicative of the transistor – not the test structure – and so the data are in as close as possible correspondence to the idealized structural representation of Figure 5.2.

#### 5.5.1 Parasitic Shells of Series Impedances and Shunt Capacitances

The topology of Figure 5.2 can be abstracted to that of Figure 5.10, evidencing nested shells of fixed ECPs around the bias-dependent core of the intrinsic model. From a specific common terminal set of S-parameters, this suggests a conceptually simple method of parasitic stripping using linear algebra, by identifying generic Y- and Z- shells of parasitic elements of Figure 5.10 in the extrinsic topology of Figure 5.2 [6,7].

Figure 5.10 Device topology emphasizing *Y–Z* shells plus intrinsic device.

The common-source two-port S-parameters describing the device are a set of four complex numbers at each measured frequency. Certainly, at any fixed, single frequency, there are far too many ECPs in the device topology of Figure 5.2 and equivalent Figure 5.10 to be identified from these four numbers. Even using data over a wide range of frequencies, it is not practical to directly estimate the values of all extrinsic and intrinsic elements at a typical active bias condition where the linear device model is most likely to be useful. It is at this point we appeal to additional knowledge of the device behavior in certain distinct regions of operation in order to help us with the parameter extraction.

#### 5.5.2 Parasitic Shell “Stripping”

##### 5.5.2.1 Using Bias Conditions to Simplify the Equivalent Circuit for Parasitic Element Extraction from Measurements

Due to the significant dependence on bias of the intrinsic ECPs, the topology of the intrinsic device can be simplified in specific “cold FET” conditions, where the transistor is not active. The total topology of the device model in Figure 5.10 then becomes more amenable to unambiguous extraction, where the parasitic elements can be more readily separated from the intrinsic elements. Under these conditions, the parasitic elements in the different shells of Figure 5.10 can be identified much more easily.

##### 5.5.2.2 Identification of the Parasitic Capacitances

We consider one of the cold FET conditions where *V*_{DSDC} = 0VDSDC=0 and the device is reverse-biased to the point where the gate-source voltage is less than the threshold voltage, VGSDC<VT. Under these conditions, where the device is not active, the device intrinsic transconductance, *G*_{m}Gm must vanish. Under this strong reverse bias condition, we can also assume the intrinsic drain-source resistance, *R*_{DS}RDS, is large enough to be neglected, which removes both of those branches from the equivalent circuit of the intrinsic device. If we further limit the characterization frequency range for the S-parameters to be far below the cutoff frequency of the device, we can also usually neglect the series inductances, and since we are ultimately interested in the imaginary part of the admittance elements in the outer shell, we can neglect the series resistances as well. The inductances and resistances will be dealt with by considering a different bias condition in Section 5.5.2.4. This assumes the value of intrinsic *C*_{DS}CDS is zero at this particular bias condition.

We are left, therefore, with the combination of outer-shell parasitic capacitances in parallel with the intrinsic device junction capacitances at this reversed bias condition. This simple approximate equivalent circuit topology is shown in Figure 5.11.

Figure 5.11 Simplified parasitic capacitance model of a FET under passive bias condition for parasitic capacitance identification.

Given the topology of the Figure 5.11, the correspondence between the 2-port linear data and the desired ECPs is most easily formulated in the admittance representation. We use the standard formula to convert the S-parameters to the Y-parameters given by (5.3), which follows from (3.36).

The following simple relationships defining the element values in Figure 5.11 in terms of the common source Y-parameters are given in equations (5.4).

Here *C*_{GSi} and *C*_{GDi}CGSiandCGDi are the intrinsic capacitances of the junction at the particular cold bias point, and *C*_{GSx}, *C*_{GDx}, and *C*_{DSx}CGSx,CGDx,andCDSx are the parasitic values that, being assumed independent of bias, are to be identified.

There are still too many unknown parameters (five) on the left side of equations (5.4), to identify them all from one set of device admittances. Therefore, we characterize *an array of devices* of physically scaled layouts, shown in Figure 5.12, of various numbers of parallel gate fingers with various finger widths, and use the resulting geometrically dependent ECP values to separate parasitic from intrinsic element values.

Figure 5.12 FET array of scaled layouts to identify parasitic elements.

Fitting the first equation of (5.4), from data for each set of devices with the same number of fingers separately, we get the plots of Figure 5.13 where the intercepts (extrapolation to zero width) provide the values for the parasitic capacitances of devices with different numbers of fingers. This interpretation assumes that the intrinsic capacitance values, extrapolated to zero gate width are zero. This is a physically reasonable approximation neglecting only fringing fields and perimeter effects that are usually insignificant for practical FET geometries.

Figure 5.13 Linear regression allows for parasitic capacitance identification.

It is a good sanity check that the slopes of the three independently fitted lines plotted in Figure 5.13, are so consistent.

Plotting the values of *C*_{GSx}CGSx versus the number of fingers, we obtain the geometrical scaling rule from the linear fit shown in Figure 5.14.

Figure 5.14 Scaling rule for shunt parasitic gate-source capacitance versus finger number.

A similar approach can be taken for the remaining parasitic elements in Figure 5.11.

##### 5.5.2.3 Stripping Off the Outer Admittance Shell

With the parasitic capacitance values of the outer parasitic shell now known, the two-port description at the device plane can be moved to the plane of the parasitic impedances.

Given the topological representation of these parasitics, the relationship between the common source two-port parameters at the Y and Z planes can be expressed most simply according to (5.5). The subtraction is element by element in the admittance representation, and it gives the common-source Y-parameters with the parasitic capacitances removed (Figure 5.15). The inverse of this difference is, therefore, the Z-parameter matrix, *Z*, at the plane of the series parasitics.

In (5.5), we have computed the common source parasitic admittance matrix, *Y*^{para}Ypara, in terms of the parasitic capacitance elements using the definition of the admittance matrix according to (5.6) and the structure of Figure 5.2.

##### 5.5.2.4 Parasitic Resistance and Inductance Extraction

We now move on to extracting the series parasitic shell containing the resistances and inductances. The strategy is similar to the capacitance parasitic extraction step of 5.5.2.2, in that we choose a bias condition to simplify the equivalent circuit, but this time the operating conditions are quite different. We will also do a matrix subtraction to remove the parasitic elements, but this time, due to the topology, we do so in the impedance domain.

###### Direct Method Based on Extreme Forward Bias Condition

A significantly forward-biased gate voltage is chosen such that there is substantial current flowing into the gate terminal across the Schottky barrier. The drain-source voltage is chosen to be zero, or, nearly equivalently, the drain current is biased to be equal and opposite to half the gate current. That is, IDDC=−IGDC2. This condition forces the drain and source current to be equal.

This DC condition is assumed to be sufficiently extreme so as to effectively short out the Schottky barrier junction, interpreted as a strongly forward biased diode with, therefore, a very large conductance. The large conductance presents an effective electrical short between this intrinsic gate node and any other node to which it is connected in the intrinsic equivalent circuit. That is, the entire intrinsic FET can be collapsed to a single node, reducing the equivalent circuit topology within the Z-shell to a simple T-topology shown in Figure 5.16.

Figure 5.16 Idealized highly forward-biased FET equivalent circuit after the capacitance shell is stripped off. The intrinsic FET is assumed to be shorted out.

We remind the reader that gate current was not explicitly accounted for in the simple equivalent circuit of Figure 5.2. We assume a large conductance only at this stage in order to identify the series parasitic elements. The final linear model will be valid only for conditions where the actual gate leakage is negligible.

From Figure 5.16, we note only six equivalent circuit elements, all series parasitic elements, remain in the total model topology, now that the parasitic capacitances have been stripped off and the intrinsic device collapsed to a point at this bias condition. These EPCs can therefore be directly identified from the real and imaginary parts of the Z-matrix of the data at this plane. This follows from the computation of the parasitic Z-matrix, given in (5.7) in common source configuration, which follows from the definition (5.8), applied to the circuit representation of Figure 5.16.

While formally (5.7) can be solved for the six ECPs at any frequency by taking simple linear combinations of the real and imaginary parts of the Z-matrix, the frequency of the measurements must be high enough to measure the inductances without too much uncertainty. A fit to (5.7) from data over a range of moderate-to-high frequencies generally provides a more robust extraction than a direct solution from data at a single CW frequency.

This method has the following drawbacks, however. The extreme forward bias condition may be too stressful for modern short gate-length devices, causing damage during the measurements. Since *R*_{D} and *R*_{S}, are physically semiconductor access resistances, and as such can be current dependent, their extraction from data at an extreme bias condition may yield parameter values that might be different from their actual values under more normal operating conditions.