Many important concepts regarding nonlinear microwave systems and an extensive discussion of nonlinear device modeling techniques were introduced in previous chapters. Now, to summarize what we have learned and to facilitate the comprehension of the presented concepts, this chapter illustrates how accurate nonlinear device models and circuit simulators can be used in the design of microwave circuits. For these purposes, the design of a typical medium-power amplifier (PA) circuit will be used as an example.
We show that the effort of considering nonlinear circuit simulation and active device models is justified as these tools reduce the complexity, and thus the time needed for practical circuit designs and their characterization. Moreover, these device and circuit representations enable the analysis of the circuit’s operation, not only via the input-output observation, as is done in the laboratory, but also via looking into every internal equivalent circuit node of the active device.
The chapter is organized in two major thematic parts.
The first part, consisting of Section 7.1, recalls some results of active device modeling from previous chapters, explaining the importance and impact they have on the predicted power amplifier behavior. Special attention will be paid to the model features that determine the most important PA characteristics: output power, drain efficiency, and AM/AM and AM/PM distortion, i.e., gain amplitude and phase profiles.
The second part, Section 7.2, details the PA computer-aided design and verification procedures. It first illustrates the roles that the nonlinear device model and a simulator can play in the various circuit design steps, constituting an aid, or even a substitute, to the laborious and expensive measurement-intensive conventional PA design procedure. Then, we will also show how simulations can be used to estimate and interpret the performance characteristics of the implemented circuit.
7.1 Nonlinear Device Modeling in RF/Microwave Circuit Design
Contrary to a low-noise amplifier, or a low-power PA design, which, nowadays, often use MMIC implementation, medium to high-power PAs rely on packaged devices mounted in a PCB. Therefore, not only do the equivalent circuit models of Chapters 5 and 6 have to be embedded in a more or less complex package model, but the designer may also face the situation of having to design a PA with a device for which there is still no available model provided by the device vendor. This is quite common in mobile communications base station design, and is aggravated in high-power (hundreds of watts peak-power) circuits whose active devices are often internally prematched. This is one field in which the frontier between active device modeling and circuit design is blurred, and so where the microwave engineer has to make a prudent choice of the best compromise between a model’s complexity (and, thus, difficulty of extraction) and accuracy, i.e., mostly the model’s capability to predict the actual device’s output power and efficiency load-pull contours and AM/AM and AM/PM profiles. As we will see, this goes all the way from the judicious choice of the equivalent circuit topology to the formulations of the iDS(vGS,vDS), Qgs(vGS,vDS), Qgd(vGS,vDS) and Qds(vGS,vDS) nonlinear constitutive relations.
To obtain a representation as close as possible to the real device, the model topology is frequently established according to our knowledge of the device’s structure and physical operation. Actually, Figure. 7.1(a) is an illustration of the geometry of an RF MOSFET, which is then translated into the equivalent circuit model of Figure 7.1(b). As discussed in Chapters 5 and 6, this model can be divided into intrinsic and extrinsic subcircuits. The former ones are associated with the channel, while the latter are the representation of the parasitic effects associated to the metallization of the die and the package.
7.1.1 The Extrinsic Subcircuit Model
Since the extrinsic elements are bias-independent, or linear, we could think that they may not be as important as the intrinsic elements for the design of a nonlinear circuit such as a power amplifier. However, these extrinsic elements play a fundamental role in the accurate prediction of output power and efficiency load-pull contours. To illustrate this, Figure 7.2 shows three different sets of load-pull contours for a commercial 240 W packaged Si LDMOS device. Figure 7.2(a) depicts the obtained load-pull predictions in which the used model is only composed of the adopted FET iDS(vGS,vDS) nonlinear model; (b) shows the updated load-pull predictions – reported at the intrinsic reference plane – when the intrinsic Qgs(vGS,vDS), Qds(vGS,vDS) and Qgd(vGS,vDS) nonlinear voltage-dependent charge models or their equivalent capacitances, Cgs(vGS,vDS), Cds(vGS,vDS), and Cgd(vGS,vDS), were also included; and, (c) illustrates the final load-pull predictions of the entire model of Figure 7.1, i.e., when also the extrinsic sub-circuit is considered.
Figure 7.2 Output power and efficiency load-pull contours of a 240 W packaged Si LDMOS device simulated at 1800 MHz in three different situations: (a) considering only the adopted FET iDS(vGS,vDS) nonlinear model, (b) considering the FET iDS(vGS,vDS) and Cgs(vGS,vDS), Cds(vGS,vDS) and Cgd(vGS,vDS) intrinsic nonlinear capacitances at the intrinsic reference plane, and (c) considering the entire model, i.e., also including the extrinsic linear elements.
Comparing the contours of Figure 7.2(b) and (c) with those determined by the nonlinear FET channel current of (a), first we should note a non-uniform stretching of the contours, in particular in high impedance values, where the output voltage excursion is higher, producing a large variation of the nonlinear output capacitance. Thus, after de-embedding the small-signal capacitance, the optimum impedances become more reactive. Finally, with the inclusion of the extrinsic elements in (c), the load-pull contours moved to a different Smith chart region.
Measuring the load-pull contours at the extrinsic reference plane, so that they can be used as a practical power amplifier design tool, usually requires a very complicated and time-consuming task of laboratory load-pull characterization. However, if we had access to a complete equivalent circuit model, we could obtain these load-pull contours through simulation, or simply determine their estimates at the intrinsic level [1,2] and then calculate their extrinsic counterparts, embedding the impedance transformation effects of the extrinsic subcircuit elements. Alternatively, the power amplifier design could be done at the intrinsic reference plane incorporating all extrinsic components into the matching networks.
The extraction of the package parasitic network requires S-parameter characterization of a dummy device, i.e., an empty package, and/or measurements of a complete device biased at extreme quiescent states, such as cut-off, or gate-channel junction forward bias at the FET’s triode region.
In high-power devices, as represented by the illustration presented in Figure 7.3(a), the intrinsic optimum impedances are so low that in-package prematching networks are often needed to transform them into manageable impedance values at the package reference plane. Unfortunately, the physical dimensions of these multifinger devices and of their connection pads, bond-wires, leads and prematching structures are often an appreciable fraction of the wavelength. Therefore, their accurate modeling cannot be accomplished with lumped elements, requiring, instead, complex electromagnetic simulations [3]. The obtained S-matrices – or their time-domain equivalent circuit representation [4] – are then included into the entire high-power device model, as illustrated in Figure 7.3(b). With these intricate prematching structures, the external reference plane moves further away from the intrinsic one, which produces a larger transformation of the load-pull contours, as shown in Figure 7.3(c). Moreover, the narrowband nature of these prematching networks strongly influences the harmonic impedances at the intrinsic reference plane, regardless of the harmonic terminations provided at the package terminals; and this significantly limits the use of harmonic manipulation for optimized PA performance.
7.1.2 Nonlinear iDS(vGS,vDS) Current Model
After prescribing the equivalent circuit topology, we now need to discuss the intrinsic elements. Of these, a realistic voltage-dependent iDS(vGS,vDS) drain current model is key for an accurate prediction of the AM/AM profile and the output power and drain efficiency load-pull contours. As explained in Chapter 6, various model formulations can be adopted, from more or less compact formulae, to complex, but systematic, neural networks. However, more important than the actual iDS(vGS,vDS) formulation is the measurement dataset from which it is extracted.
7.1.2.1 iDS(vGS,vDS) Current Model Extraction
In devices that suffer from obvious thermal, or even trapping, effects, such as power FETs, dc and RF data are not consistent [5]. Hence, either we have an NVNA to measure the device in a wide set of operating conditions [6] and then rely on the simultaneous nonlinear optimization of dc and drive-level and load dependent RF data described in Chapter 6, or we try more conventional data collection procedures such as bias-dependent S-parameter data. In that case, iDS current is obtained by integration of the transconductance Gm(vGS,vDS) and output admittance Gds(vGS,vDS) profiles measured under pulsed bias conditions.
As an example, in Figure 7.4 we can observe pulsed dc I/V curves, from a GaN HEMT device, and the ones obtained from the Gm and Gds integration over vGS and vDS, when the applied pulses were incapable of producing isodynamic measurements. As expected, if the thermal and trapping states are not the same for all tested bias points, the obtained I/V curves will be different, being impossible to fit these measurements to any single iDS(vGS,vDS) model expression.
On the contrary, if a prepulse is used to set the traps’ state, guaranteeing that the thermal and trapping states do not change for all measured bias points [7] – obtaining, this way, isodynamic measurements – the I/V curves will be the same, either directly measured from the iDS pulses, or obtained from the Gm and Gds integration, as shown in Figure 7.5.
Figure 7.5 I/V curves of a GaN HEMT device (a) obtained by Gm(vGS,vDS) and Gds(vGS,vDS) integration – referred to as “IDS from gm” and “IDS from gds”, respectively – and (b) with the direct pulsed I/V method, when the measurements are guaranteed to be isodynamic.
7.1.2.2 Impact of the iDS(vGS,vDS) Current on the PA Output Power and Efficiency
The knowledge obtained from modeling these thermal and trapping effects also helps us to understand how they affect the I/V curves, which may guide us later during our PA design.
For instance, it is known that, when a high vDS peak voltage is applied to the device, the maximum iDS current, IMAX, decreases and a threshold voltage, VT, displacement is observed due to the trapping effects [5–8]. Consequently, the iDS(vGS,vDS) curves will be different if we consider the I/V curves pulsed from 0 V or from a high peak quiescent voltage, which, in turn, will modify the optimum power and efficiency load terminations, as show in Figure 7.6(a).
Figure 7.6 Illustration of the (a) trapping and (b) thermal effects’ impact on the optimum power load estimation.
Thermal effects will also produce an IMAX drop when the device operates in large-signal mode, because of the increased device’s dissipation and temperature, and thus decreased channel conductivity [9]. Therefore, if we only consider the I/V curves measured at room temperature, the estimation of the optimum power and efficiency impedances could also be different from the real ones obtained when the high-power signal is applied to the device, and thus its temperature is increased, as illustrated in Figure 7.6(b).
7.1.2.3 Impact of the iDS(vGS,vDS) Current on the PA AM/AM Distortion
Having discussed the implications of the iDS(vGS,vDS) drain current model on the maximum output power and efficiency, we will now take a look at the distortion arising from this nonlinear voltage-controlled current source. For that, we will remove the nonlinear intrinsic capacitances – i.e., replace them by their linear versions – and compare the simulation results with the ones obtained when the full nonlinear model is considered.
Figure 7.7 shows this comparison for three different PA operation classes corresponding to shallow class AB, class B, and shallow class C. Looking into these results, we can conclude that the nonlinear iDS(vGS,vDS) current is, indeed, the main contributor to the AM/AM characteristic of a PA, because only slight differences are observed due to the input and output mismatches produced by the nonlinear capacitances. Actually, in [10] it is explained how each of these curve shapes can be related to particular iDS(vGS,vDS) model features such as the FET’s soft turn-on and its saturation to triode region transition.
7.1.3 Nonlinear Intrinsic Capacitance Models
7.1.3.1 Nonlinear Capacitance Models Extraction
The problems experienced with the iDS(vGS,vDS) model extraction, which were related to the thermal and trapping effects, are also present in the identification of the intrinsic nonlinear voltage-dependent charge sources. Therefore, to guarantee an isodynamic extraction, the double-pulse bias-dependent S-parameter measurements we adopted for the iDS model extraction should still be used for the capacitances.
Figure 7.8 shows typical Cgs(vGS,vDS), Cds(vGS,vDS), and Cgd(vGS,vDS) profiles. A high variation with vGS is observed in the Cgs profile around the threshold voltage, whereas Cgd and Cds only present a significant variation – with vGD and vDS voltages, respectively – when the device becomes operated in the triode region.
These variations will detune the output efficiency load-pull contours predicted when only the I/V curves are considered, as was seen in Figure 7.2. In addition, for advanced PA architectures, such as the Doherty PA, where it is necessary to compensate the delay between the main and auxiliary amplifiers [11], the variation of these capacitances will make it more difficult to determine the correct delay that should be used for large-signal operation. Moreover, these variations will have a severe impact on the AM/PM PA characteristic, as we will explain next. Consequently, the nonlinearity of the intrinsic capacitances and their accurate modeling should be also taken into account for a successful PA design.
7.1.3.2 Impact of the Intrinsic Capacitances on the PA AM/AM and AM/PM Distortion
With respect to the nonlinear distortion induced by the intrinsic capacitances, we have to distinguish the PAs based on the Si LDMOS and GaN HEMT, the two main RF power transistor technologies used for mobile communication base stations, since they present significant differences in their normalized capacitances. Si LDMOS devices usually have higher Cgs and Cds capacitances and lower Cgd feedback capacitance, when compared with those of GaN HEMTs [12].
Another aspect that we should take into consideration when assessing the impact of Cgd nonlinearity in the PA performance is that this can be viewed as two independent effects. On one hand, Cgd is a nonlinearity in itself because, as seen Figure 7.8(c), it manifests a noticeable variation with the vGD voltage. But, on the other hand, it should be noted that, even if Cgd were linear (i.e., constant or bias independent), it would still constitute a source of nonlinearity. Because Cgd is reflected, through the Miller effect, to the input as Cgd(1 − Av), and to the output as Cgd(Av − 1)/Av, and the voltage gain, Av, will have to vary due to the inevitable PA gain compression, the effect of Cgd will also be nonlinear. Measurements and simulations of microwave FET amplifier circuits have shown that, perhaps unexpectedly, the input Miller reflected Cgd nonlinearity is more significant than the direct Cgd(vGD) nonlinearity [10].
To understand the underlying reasons for this surprising result, equation (7.1) gives the value of the intrinsic vgs voltage when the PA is excited by a sine wave of amplitude Vs(ω). Because the equivalent nonlinear capacitance that appears at the FET’s input terminals is composed by this input Miller reflected Cgd along with the nonlinear Cgs(vGS) capacitance, the intrinsic Vgs phasor voltage will vary, in amplitude and phase, with the amplitude drive, A, according to
(7.1)where Cgs0 is the time-varying Cgs(t) averaged over one RF period [10].
Figures 7.9 and 7.10 show the normalized (in a per watt basis) Cgs0 and the Cgd,Miller dependence with the amplitude for Si LDMOS and GaN HEMT based PAs, respectively. The selected VGS bias points were the ones corresponding to the same three operation classes used for the iDS(vGS,vDS) distortion analysis. Although both PAs present similar capacitance profile shapes, the input Miller reflected Cgd value for Si LDMOS PAs is almost insignificant when compared with the Cgs0, whereas in the GaN HEMT PAs it is the major contributor to the input capacitance variation. This means that in GaN HEMT PAs, the input capacitance decreases whenever the gain compresses or it increases when a gain expansion is observed.
Figure 7.9 Normalized (per Watt) profiles of (a) the Cgs0 component and (b) the input Miller reflected Cgd for a Si LDMOS based PA.
Figure 7.10 Normalized (per watt) profiles of (a) the Cgs0 component and (b) the input Miller reflected Cgd for a GaN HEMT based PA.
As far as the PA output node is concerned, since the voltage gain is normally very high, the output Miller reflected Cgd variation [Cgd(Av − 1)/Av] is almost negligible. Thus, the Cds variation will be the main contributor to the phase shift on the fundamental vDS voltage, according to equation (7.2).
(7.2)The Cds0 capacitance variation for both Si LDMOS and GaN HEMT based PAs is depicted in Figure 7.11. Again, although the capacitance profile shapes of both devices are very similar, their values are completely different, with Cds0 being much higher for Si LDMOS based PAs. Actually, for GaN HEMT based PAs, the Cds0 variation is so small when compared with the input capacitance variation (see Figures 7.10 and 7.11) that it will be insignificant for the overall amplitude nonlinearity (AM/AM) or phase shift (AM/PM) of the PA.
Figure 7.11 Normalized (per Watt) profiles of the Cds0 component of (a) Si LDMOS and (b) GaN HEMT based PAs.
Because the iDS(vGS,vDS) nonlinearity is the dominant contributor to the PA amplitude, AM/AM, distortion, the main effect of capacitance nonlinearities is on the amplitude dependent phase shift, AM/PM. But, contrary to what happens with the iDS(vGS,vDS) nonlinearity, and thus with the amplitude distortion, these two technologies present quite different intrinsic capacitance variations. Hence, Si LDMOS and GaN HEMT based PAs evidence significantly distinct AM/PM characteristics, as shown in Figure 7.12. For Si LDMOS, the Cds0 variation is the major contributor to the AM/PM distortion, producing an almost phase-lagging behavior for all operation classes; only a slight phase-leading behavior is presented at the mid-power region for class AB due to the initial Cgs0 reduction. Conversely, the AM/PM distortion of GaN HEMT PAs is mostly determined by the phase shift imposed on the Vgs phasor voltage, due to Cgs0 and input Miller reflected Cgd variation. Therefore, since this capacitance variation is tied to the voltage gain, the AM/PM characteristic presents an opposite behavior to the AM/AM characteristic, as can be seen when we compare the AM/AM behavior shown in Figure 7.7 and the AM/PM of Figure 7.12(b).
7.1.4 Device Model Implementation in Commercial Microwave Circuit Simulation Platforms
To finalize this section devoted to illustrate the use of nonlinear models and computer-aided design tools in predicting the major RF characteristics of microwave devices, we now show how the above nonlinear models can be implemented in the available commercial simulators, such as the Keysight Technologies Advanced Design System, ADS [13], and the Applied Wave Research Microwave Office, MWO [14]. For that, we will use simple model formulations of the bidimensional nonlinear iDS(vGS,vDS) current and the assumed one-dimensional gate-source charge, Qgs(vGS), or capacitance, Cgs(vGS).
For the iDS(vGS,vDS) formulation we will use a model (7.3a) consisting in the product of (7.3b) and (7.3c), which describe the iDS dependence on the vGS and vDS voltages, respectively. Figure 7.13 shows the I/V curves of this simple model and the respective derivatives, Gm and Gds.