## Abstract

Basic amplifier stages are described in a somewhat cursory fashion. We use circuits that are familiar to most readers and present the analysis in a way that conforms to the estimation analysis described in Chapter 1. This way the reader will encounter familiar calculations in a different framework. The estimation analysis is also applied to nonlinear extensions of the common transfer function expressions. The chapter contains design examples and a set of exercises to ensure that the reader understands the basic concepts.

### 2.1 Introduction

In this chapter we introduce basic transistor amplifier stages and use them as a starting point to describe the estimation analysis method. For more details on the transistors and the models used we refer to Appendix A.

For the reader familiar with the discussion in books such as [1–5] this chapter should not pose any difficulty.

Fundamentally, all we do in all these simplifications is to linearize the transistor or amplifier at its bias point and draw conclusions about fundamental properties such as gain and impedance. We ignore the body effect for clarity, by assuming that the body is always tied to source in all transistors.

In addition, we will also venture into the world of weak nonlinear effects and show how these gain stages can be analyzed with simple extensions to the standard linearization techniques, all in line with the estimation analysis method.

We start the chapter with a section on single transistor gain stages and continue with a few well-known two transistor stages. For brevity, we will focus on CMOS transistors, but other transistor types such as bipolar can easily be analyzed in the same way. We go through some design examples in detail in order to use the results in the later chapters.

### 2.2 Single Transistor Gain Stages

Single CMOS transistor gain stages are traditionally divided into three groups: common gate (CG), common drain (CD), and common source (CS) stages. The word common refers to the terminal that is common to both input and output signals, which can be either voltage or current. We will describe them one by one in this section. We will keep the discussion at a general level; the precise expression for the currents’ dependence on terminal voltages does not matter. Only in the final expression, when we are after something specific, do we use specific current voltage relationships described in Appendix A.

#### CG Stage

The common gate (CG) stage is an amplifier where the gate node is tied to a fixed voltage, possibly with some impedance in series. The input signal enters through the source terminal and exits at the drain terminal. The signal is best described as a current.

Here we will solve for gain and input impedance.

##### Simplify

We assume the transistor is in saturation so we will ignore the drain gate capacitance. We also assume the drain source impedance is sufficiently large so as not to affect the gain; and finally we assume the output load to be zero ohms. The transistor model in Figure 2.1 shows our assumptions. When comparing with the literature this could be seen as an over-simplification, but we are only interested in the dominant parameters that set the gain and input impedance so that the simplifications are an adequate approximation for an estimation analysis. To calculate the gain we will in addition linearize the transistor around its bias point.

Figure 2.1 Common gate transistor stage with linearization.

We find for *Z*_{G} = 0 → *v*_{g} = 0ZG=0→vg=0 and by applying Kirchoff’s current law (KCL) at the output node

*i*

_{out}=

*g*

_{m}(

*v*

_{g}−

*v*

_{s}) = −

*g*

_{m}

*v*

_{s}.

We also know

*i*

_{in}= −

*v*

_{s}

*jωC*+

*i*

_{out}.

##### Solve

By solving for *v*_{S}vS we find

or

We see for low frequencies that the input current goes straight through to the drain or output, but for higher frequencies the capacitor between the gate and the source will act as a short, effectively grounding the current and leaving nothing to the output. The transition point where |*jωC*| = *g*_{m}jωC=gm is a rough estimate of the transition frequency or *f*_{t}ft. A more detailed model can be found in [3]. Here we get

This is an important figure of merit for high speed designs and the expression (2.1) is a convenient rule of thumb.

What about the input impedance? We now have to rewrite *i*_{in}iin in terms of *v*_{s}vs:

*i*

_{in}= −

*v*

_{s}

*jωC*+

*i*

_{out}= −

*v*

_{s}

*jωC*−

*g*

_{m}

*v*

_{s}= − (

*jωC*+

*g*

_{m})

*v*

_{s}.

We find

Imagine now there is a gate impedance, *Z*_{G}ZG. We find

or

To find the input impedance we need to rewrite *i*_{in}iin in terms of *v*_{s}vs.

We the find after a simple rearrangement

##### Verify

As the reader no doubt recognizes, these calculations can be found in any standard electronics book, but here we have made some simplifications beyond that which is normally done. This is all in line with the estimation analysis idea. We are only seeking a model that is simple enough to capture the essence of what we want to know, in this case gain and input impedance. The calculations in this chapter are easy to verify in the literature. We will encounter more complex situations in Chapters 4–7.

##### Evaluate

We have followed the estimation analysis method and we recognize the calculations from similar examples in the standard literature. To investigate the meaning of these expressions we need to go to various limits of key parameters. This is also often a way to sanity check the answer.

Let us look at the gain

If *ω* → 0ω→0 we see the gain *A* → 1A→1. For high frequencies, *ω* → ∞ω→∞ we see the gain *A* → 0A→0. Obviously, when *g*_{m} → 0gm→0 the gain *A* → 0A→0.

Similarly, for the input impedance

We see an interesting relationship between the gate impedance and its reflection at the source. When ω2π≪ft the gate impedance will be rotated by 90 degrees so a resistor in the gate will look like an inductor at the source, a capacitor will look like a resistor, and, most disturbingly, an inductor will look like a negative resistor, a kind of gain that can cause instabilities. For the limit *ω* → 0ω→0, the input impedance is simply 1/*g*_{m}1/gm. In the other limit, *ω* → ∞ω→∞ the input impedance is simply *Z*_{G}ZG, which makes sense since in this case the gate capacitance shorts the 1/*g*_{m}1/gm from the transconductor.

#### CD Stage

For the common drain (CD) stage the input voltage goes to the gate of the transistor and the output is picked off of the source. It is often referred to as a source-follower circuit, or follower for short. The basic circuit configuration can be found in Figure 2.2.

Figure 2.2 Common drain transistor stage with linearization.

We will solve for gain and input impedance.

##### Simplify

First we will simplify the situation in a similar fashion to the CG stage.

##### Solve

The output of the source will look like

*v*

_{out}= (

*i*

_{d}+ (

*v*

_{in}−

*v*

_{out})

*jωC*)

*Z*

_{L},

*i*

_{d}=

*g*

_{m}(

*v*

_{in}−

*v*

_{out}).

After a simple rewrite

The input impedance is now calculated by getting the input current

and rearrange to find

##### Evaluate

Let us look at the expression for gain, equation (2.2). When ω2π≪ft we see

For large load impedances, *g*_{m}*Z*_{L} ≫ 1 *v*_{out} → *v*_{in}gmZL≫1vout→vin. In the other extreme, *Z*_{L} → 0ZL→0 we get *v*_{out} → 0vout→0, the output is simply shorted to ground.

As in the common gate stage we see the input impedance sees a 90 degree rotation of the impedance at the output, but this time it goes the other way: an inductor looks like a resistor, a capacitor looks like a negative resistor and a resistor looks like a capacitor. In fact for many input stages in narrow-band applications, like cellular phones, this property is a really nice way to create a low-noise input termination with the use of an inductor at the source of the input stage. The input stage will rotate this inductor to look like a real impedance with little noise(!). The remaining capacitor is often resonated out by a series inductor but that is a topic for another book.

#### CS Stage

The common source stage is perhaps a configuration that one often encounters early on in one’s career. A common setup can be seen in Figure 2.3.

Figure 2.3 Common source transistor stage with output load.

We will calculate gain and input impedance again.

##### Simplify

The output is a voltage when loaded with an impedance and the input is a voltage. We follow a similar linearization technique to that we had before, but this time we will include the gate drain capacitance, *C*_{gd}Cgd. We then have to solve KCL at the drain and source, we assume the gate driving impedance is zero.

##### Solve

We have for the basic parameters

*i*

_{d}=

*g*

_{m}(

*v*

_{in}−

*v*

_{s})

*v*

_{s}= 0

*i*

_{s}=

*i*

_{d}+

*jωC*(

*v*

_{in}−

*v*

_{s}),

*i*

_{out}=

*i*

_{d}+

*jωC*

_{gd}(

*v*

_{out}−

*v*

_{in})

*v*

_{out}= −

*i*

_{out}

*Z*

_{L}

We find

Upon substitution of *v*_{out}vout from the expression of gain above we can rewrite

##### Verify

As before, this is a standard calculation in [2] but here we made even further simplifications to get an estimate of the gain and impedance.

##### Evaluate

We see for low frequencies the gain, *A*_{gain} = − *g*_{m}*Z*_{L}Again=−gmZL, but there is a cross-over frequency where the gain transitions at *ω* = *g*_{m}/*C*_{gd}ω=gm/Cgd, in effect the major output current is supplied by the gate drain capacitance *C*_{gd}Cgd instead of the transistor gain. In the literature this is known as a right half plane zero. The input impedance is essentially a two-pole system due to the two capacitors. We see for low frequencies the total capacitance is the sum of *C*C and *C*_{gd}(1 + *g*_{m}*Z*_{L})Cgd1+gmZL, the gate drain capacitance has been amplified a factor (1 + *g*_{m}*Z*_{L})1+gmZL. This effect is known as the Miller effect, the gain across a capacitor will amplify the capacitors value, increasing the effective load.

#### Nonlinear Extension

We can now employ the same technique to examine nonlinear extensions. In general one needs to employ Volterra series for electronics systems instead of the more commonly known Taylor series. This is due to the fact the systems we are considering have memory in that the output signal depends to some degree on what happened at earlier times in perhaps other parts of the circuit. The simple stages we will look at here have relatively high bandwidth in small geometry CMOS technologies, *f*_{t} > 100 GHzft>100GHz so we will assume a Taylor series expansion is appropriate. It often turns out to be quite useful, but care must be taken and the important verification step must be completed to make sure we do not fool ourselves and are better served with Volterra series.

For Taylor series we can write the output as a polynomial expansion of the input:

Here

The coefficients can be calculated in several different ways: (1) One can sweep the DC bias point in a simulator and take the appropriate derivatives. (2) One can do a Fourier transform of the output when the input is a single tone sinewave, the linear and higher-order coefficients can be found from the harmonic powers. When relating the two methods keep in mind the mixing effect of the Taylor series when using sinusoids, *V*_{0} = *A* sin *ωt*V0=Asinωt:

For example, the second-order term splits into a DC component and a second harmonic component. To find the size of the second harmonic term one needs to divide the second-order derivative of the transfer function by a factor of four. A factor of two comes from the Taylor expansion and another factor of two from the mixing action, where half the amplitude goes to DC and rest into the second harmonic. This is similar for higher orders but obviously more complex.

##### CD Stage

We will follow the CD stage discussion and make a first order correction to the gain calculation.

We start with

*v*

_{o}=

*g*

_{m}(

*v*

_{in}−

*v*

_{out})

*Z*

_{L},

where we assume the frequencies of interest are far below *f*_{t}ft, and we are using Figure 2.2 for reference. In this section we limit ourselves to gain calculations.

###### Simplify

We will first simplify the discussion by assuming the drain source conductance is negligible. We use the following expression for

Finally, the load *Z*_{L}ZL is for this discussion a real impedance.

###### Solve

We now write

and put this into the expression

Now we identify terms of the same order on each side of the equal sign. We find

We solve for