## Abstract

The observations from the is applied specifically to integrated circuit situations, where transmission line effects, inductors, capacitors and S-parameters are discussed using the estimation analysis method. Many useful formulae are derived that are used to design real world inductors and estimated parasitic capacitances. Also a brief overview of the connection between the printed circuit board and on-die applications is presented as well as a summary of the current state of detailed modeling of interconnect effects. The theoretical underpinnings behind common shielding techniques is discussed using the estimation analysis in the last part of the chapter. It is followed by design examples and exercises.

### 5.1 Introduction

This chapter discusses applications of electromagnetism mainly in the context of integrated circuits with the help of estimation analysis. The main purpose of this chapter, as with the other chapters, is to showcase estimation analysis. We will think of ways to simplify a problem, verify that we capture the relevant properties, and then evaluate the result. At the end of the chapter we will use these simplified models in several design examples to establish a starting point for fine-tuning in simulators.

In recent decades, high frequency electromagnetic effects have become increasingly important for on-chip circuit design with the increase in speed and required processing power. Compared with general microwave situations, the length scales under consideration are smaller than typical wavelengths and this provides some natural simplifications for the estimation analyses. Since we are also approaching speeds where the wavelength is comparable to the circuit size scales, we will discuss short wavelength effects in this chapter. Much of what we will be discussing has been touched upon, one way or another, in references [1–18].

We start the chapter with a discussion of the connection between printed circuit board designs and on-die designs. Thereafter we discuss transmission lines and distributed effects. The concept of S-parameters can often be confusing, and we take some time to discuss it from an estimation analysis perspective. This is followed by a section on capacitors, and since this is generally well known, we will be somewhat brief in this discussion. Traditionally they were designed as overlapping metal plates, but with the advance of small geometry CMOS this topology is no longer used much. Instead, MOM (metal–oxide–metal) capacitors where thin, inter-digitized fingers provide the desired capacitance are used. The advancement in lithography has made it possible in modern CMOS technologies to produce such capacitors with much smaller process variation than earlier varieties, and we will briefly discuss the circuit implications. Of course, gate-over-oxide constructions are another approach, and we address this in the section on metal plates. Thereafter we discuss on-chip inductors, where we model various idealized situations and, by removing these idealizations, come to a realistic model of on-chip inductors where capacitance and resistance are also major contributors.

### 5.2 Connection to PCB Designs

Printed circuit board (PCB) designers have encountered high speed, or distributed, effects for many years not only through fast clock frequencies but also through fast edge rates, and it is only recently that on-die circuit designers have been forced to take such effects into account. On die, the convenient long wavelength approximation was for a long time sufficient for the interconnect modeling. Normally, distributed effects became important in the package interface. Nowadays, these effects have creeped into the on-die interconnects due to the ever increasing need for higher and higher speeds, and a thorough understanding of these kinds of effects has become mandatory. A good description of the problems can be found in [7]. Here many of the electromagnetic properties we found in Chapter 4 are discussed more fully in connection to the PCB design. We will mention just a few of the similarities here and point to what is different, and where different approaches may sometimes be necessary.

#### Interconnect Scale vs Wavelength

Distributed effects start to become prominent when the wavelength in question, *λ* = *c*/*f*λ=c/f where *c*c is the (local) speed of light and *f*f the signal frequency, is similar to the physical length. The important comparison scale turns out to be even smaller than *λ*λ and we will derive such results in this chapter. Imagine we have a 10 GHz signal traveling in a uniform medium with a permittivity of 4, we find *λ* = 1.5 ⋅ 10^{8}/10^{10} = 1.5 cmλ=1.5⋅108/1010=1.5cm. On a printed circuit board this is a very small distance. On die, this is fairly large. Ten GHz used to be a respectable frequency, but now imagine a 50 GHz signal. The wave length is 3 mm. A modern high speed integrated circuit can easily be a centimeter or two per side, of which the analog portion is significant. It is then clear that issues such as proper termination to avoid reflections is important.

#### Ground Planes

These distributed effects were understood very early on in the development of the circuit board, and the concept of proper ground was developed. A modern circuit board can have many tens of layers of copper, each of which is perhaps 15 µm thick, and every second layer is typically used either as a ground or supply plane. On die there can also be more than ten layers, but in contrast to the circuit board system the thickness is only significant (greater than the skin depth) for a few of the top layers. Using lower metals for the ground/return path is woefully inadequate. Instead, co-planar wave guides or multilayer ground planes are commonly used.

#### Vias

A circuit board via consists of a top/bottom pad and a thin metal cylinder. The pad looks capacitive and the thin cylinder looks inductive, and it can also exhibit distributed effects. An on-die via is simply a stud, often made of tungsten, and its resistance can be significant. One needs to make sure there are plenty of vias when significant current is in play.

#### Summary

As a short summary of similarities and differences between PCB work and on-chip design, we have:

## Similarities:

Length scale vs wavelength

Need for proper termination

## Differences:

Thickness of metal layers

Resistance of vias

### 5.3 Recent Progress in the Literature on Signal Integrity On-Chip

Over the last several decades there has been a continual need for increased communication speed. Looking at the state of the art a few decades ago, it was not obvious that on-chip inductors would ever be prominent. But the work of the design group under Prof. Robert Meyer at University of California at Berkeley made clear that on-chip inductors have significant advantages. With the ever smaller footprint, the size of inductors can sometimes be prohibitive, but the increase in required speed and thus smaller needed inductances make inductors a key component in high speed designs, where low phase noise oscillators are obvious circuit applications. At speeds in the 100s of GHz range, the problematic passive device is no longer the inductor, which is now very small, but rather the parasitic resistance of capacitors that causes degradation.

This “need for speed” has generated faster and faster integrated circuits, and we are now at the point where the circuit size is of the same order as the wavelength of the signal frequency we are trying to process. The interest in careful modeling of interconnects has likewise increased and several approaches have emerged. For one, accurate and fast simulators that can handle this size and frequency are constantly being developed and improved. Many of the modern simulators have user-friendly interfaces that facilitate setup and simulation. A word of warning to the user, however: oftentimes there are assumptions more or less hidden inside these simulators that may or may not be helpful in solving the problem one is addressing, and one would be wise to spend a good deal of time understanding the inner workings of the tool before embarking on large simulations. Second, the need for accurate analytical understanding has increased in lockstep with simulator developments. Researchers have developed complex models, and we will present an overview of this development in the next section where the focus is on inductor modeling; see also [19] for a recent overview of the field.

#### Inductor/Interconnect Modeling

Inductors have a high impact on high frequency performance and their modeling is critical to the success of such circuits. One difficulty with inductor modeling is it can take a bit of time to find the right size combination through field solver iterations. In fact, this is one reason that a good initial size estimate, which we will describe later in this chapter, is important. In the literature, the search for accurate inductor modeling is proceeding along several lines of inquiry. One possibility is to use foundry-supplied inductor libraries (see [20–22]), which tends to limit the ability to use an optimal size, but if one finds a reasonable candidate one has access to measured data, which is reassuring from a performance perspective. Another trend is to create various detailed analytical models as in [23–26], *π*π-models as in [27–30], or 2 ‐ *π*2‐π models as in [31] to predict inductor performance. There is also [32], where regularization theory is applied to obtain more detailed analytical mapping functions. Another direction was proposed by [33], where machine learning techniques are used to build inductor models. The accuracy is improved by only optimizing promising inductor candidates in EM-solvers instead of simulating each possible inductor, as in [34]. Another approach uses a set of EM-simulated inductors as the design space and the optimal inductor is chosen based on various constraints, as in [35, 36]. The arrival of 3D integrated circuit topologies has generated much work relating to through-silicon-vias (TSV), as in [37–40]. These topologies are there to process data faster in that with the help of TSVs, more data can be transferred vertically, which means a much shorter physical distance and less signal loss is possible.

We have highlighted a handful of situations where several groups have attempted to construct detailed models.

In this chapter we will apply the lessons from Chapter 4 to build useful simple models where the physics of, say, an inductor play a central role. It turns out that having the intuition built from such models is very useful in understanding real situations and can generate a good initial starting point for field solvers.

### 5.4 Transmission Line Theory

#### Basic Theory

The focus in this chapter is integrated circuit applications, and here, in general, transmission line effects are not important due to the small length scales involved. However, there are instances, for example inductors, where basic knowledge of transmission line theory is important. We will therefore discuss the basic theory here using estimation analysis, and we refer the reader to the many excellent discussions of the full theory in [2, 5–7, 13].

##### Simplify

A transmission line has essentially two components, one signal conductor and at least one return path as in Figure 5.1.

Figure 5.1 Transmission line components.

As we discussed in Chapter 4, this type of structure carries a certain inductance and resistance per length and a certain capacitance to ground per length. In addition, there is a loss in the dielectric medium that we will ignore here. We will model this as a simple RLC filter, as in Figure 5.2. We ignore any loss in the dielectric medium itself, often modeled as a shunt resistor to ground. We are interested in estimating effects such as gain and impedance on-chip, and for common materials inside integrated circuits this loss is negligible.

Figure 5.2 Basic transmission line modeling.

##### Solve

We can now analyze the voltages and currents using Kirchoff’s current/voltage laws:

By dividing by Δ*x*Δx and go to the limit Δ*x* → 0Δx→0 we find

We now use the assumption we are in a steady-state condition where the time variation scales as *e*^{jωt}ejωt. The equations then look like

Now taking the derivative with respect to *x* and combining the two we find

The constant in front of the current and voltage terms is known as the propagation constant, γ=R+jωLjωC. The solution is well known

Where the + refers to a wave going in the positive *x*-direction and the – refers to a wave going in the negative *x*-direction. We can use (5.1) above to write the current as

We now see we can identify a characteristic impedance as

We find

Let us now terminate the transmission line with a load *Z*_{L}ZL at *x* = 0x=0. We then can define an impedance as a function of *x* as

At *x* = 0x=0 we get

We now find

** Γ** is known as the reflection coefficient. We can now write

For *R* = 0R=0 this simplifies to

Where we have complied with the norm in the literature and refer to *x*x as –*x*–x. Let us now look at the special case where *Z*_{L} = 0ZL=0 and *R* = 0R=0. We have Z0=L/C

which approaches

We see that when *Z*_{L} ≪ *Z*_{0}ZL≪Z0 the transmission line looks inductive with a total inductance *Lx*Lx. We need to keep this fact in mind when we discuss inductors, because we must not terminate an inductor at high impedance. We will come back to these equations.

Naturally, for the opposite case where *Z*_{L} = ∞ZL=∞ we find

When terminated with an open the transmission line looks like a capacitor.

It is also instructive to see from (5.6) that at

The impedance goes to infinity. Above this length the impedance changes sign and becomes capacitive in the case of an inductor. This is known as a *λ*/4λ/4 resonance. There are also resonances at odd integer multiples of this length scale as is clear from (5.6).

CAUTION: One of the difficult parts of microwave engineering is the fact there can be many solutions to Maxwell’s equations. For a given boundary there can be many possible modes when the wavelength is similar to the size of the structure. Identifying these modes and removing the unwanted ones is among the major tasks in microwave engineering. For our particular case of a terminated transmission line, sometimes the symmetry or ground plane or other neighboring conductors can cause the electrical length of a *λ*/4λ/4 resonance to be different from what one would expect from a simple trace length calculation. For instance, a single loop inductor can be seen as a transmission line with its own return path where the halfway point, the termination, is a short. The electrical length will then be half of the physical length of the inductors coil. We will not address the precise root cause of such situations here since it is outside the scope of the book, but we encourage the reader to always verify the resonance location with a simulator. The good news is when the simulator does not agree with a naïve length calculation, it will find a length that is shorter by some integer factor. The resulting resonance frequency is thus higher than one would expect. Here, our calculations will always use the simulated resonance length if it is different from a simple trace calculation.

##### Verify

This is a standard result that, if not expressly given in the many books discussing this subject, can easily be confirmed. See for example [2, 5–7, 13].

##### Evaluate

The impedance of a transmission line depends heavily on its characteristic impedance as well as on how it is terminated. This is most clearly seen in the *λ*/4λ/4 effect, where the load impedance is effectively inverted when looking from the source point. If one terminates the transmission line with a short it will look inductive when the electrical length is short compared with wavelength, and if one terminates with an open the transmission line will look capacitive.

A transmission line terminated at low impedance, say 0 ohms, looks like an inductor when size ≪ wavelength. A high impedance termination causes the line to look like a capacitor when the size ≪ wavelength.

A *λ*/4λ/4 resonance is a situation where the length of the conductor is one-quarter of the wavelength. This will transform the impedance at the termination inversely.

##### Summary

We have applied the estimation analysis to the fundamental concept of a transmission line and demonstrated that we can reach the known solutions with simple mathematical manipulations.

### 5.5 S-Parameters

Scattering parameters or S-parameters are a fundamental tool in microwave engineering. For the electrical circuit engineer they can often be difficult to conceptualize, and we will show that we can define them in circuit theory (long wavelength approximation) where they are easier to understand. From there a short wavelength extension can be made. We again follow the steps of estimation analysis and build a simple model we can solve to demonstrate some fundamental properties.

We will start with the general definition and refer the interested reader to literature for the details behind them. The discussion follows closely what is often referred to as generalized S-parameters or power waves (see [2]), but here we make the additional assumption that the termination resistor is the same both at the source and the sink, and the degradation is modeled as an impedance between these points. We will then look at a simple circuit version of these parameters and show through some examples how they behave and are related to more familiar concepts such as bandwidth. The last section will discuss the short wavelength generalization.

#### Definition

From the picture S-parameters are defined as the ratio of incoming or outgoing wave amplitudes in different ports (Figure 5.3).

Figure 5.3 Multi-port system showing in-/outgoing waves.

For example, *S*_{11} is the ratio of the outgoing wave amplitude to the incoming wave amplitude when all other ports are 50 ohm terminated. *S*_{21} is the ratio of outgoing wave amplitude at port 2 divided by the incoming wave amplitude at port 1, all other ports being terminated to 50 ohms. Notice the concept of outgoing and incoming waves: this is a concept with meaning in the short wavelength approximation but it has no natural meaning in the long wavelength limit. Let us keep this in mind in the following discussion.

##### Simplify

We will now simplify the situation to the circuit world or long wavelength approximation. Let us consider the following simple picture (Figure 5.4).

Figure 5.4 A simple model of an input configuration.

This is a voltage source in series with two resistors. The voltage at point “*v*_{out}” is clearly *v*_{s}/2vs/2 at all times. What if we change the load resistor by adding a resistor *R*R in series (Figure 5.5)?

Figure 5.5 A simple model of an input configuration with an additional series resistor.

##### Solve

Now the output voltage will be

We can manipulate this in the following way

where we have defined an “incoming” and “outgoing” wave. In this context *S*_{11} is simply

We see that if *R*R is zero, *S*_{11} is zero. Let us think of a more complicated situation where the load consists of a cap shunting a 50 ohm resistor (as in Figure 5.6):

Figure 5.6 A simple model of an input configuration with a shunting capacitor.

We find

We see here again we can define *S*_{11} and find

For small *C*C we see *S*_{11} is zero, for large *C*C *S*_{11} = 1. What about *S*_{11} and bandwidth of the load itself? At bandwidth we have by definition *R*_{t}*ωC* = 1RtωC=1 and we see for this case

How far from the bandwidth do we need to be to get *S*_{11} = −20 dB?

which is ~5 times the bandwidth of the unterminated input! The reader should by now appreciate the difficulty in getting low return loss for a given system.

What about the other S-parameters? Let us look at *S*_{21} using the model in Figure 5.7.

Figure 5.7 A simple model of an input configuration with a series source resistor.

Here we look at the termination as ideal *R*_{t}Rt ohms and the driving impedance is different compared with our earlier discussion. We have with a resistive driving impedance

The energy that goes into the output load is simply the outgoing wave.

At the input we see the driving impedance as *R*_{t}Rt ohms with a load that looks nonideal. With a real nonideality we see

We identify again the first terms as the incoming wave and the last term as the returned amplitude.

We can now identify the various S-parameters:

We see now

For this sum to equal one we are missing a term

What happened to it? Since the square of the S-parameters has something to do with power, let us take a step back and think about this situation in terms of power. We have a current

How much power is being burnt in the various resistors?

Let us normalize this to the power burnt in the load termination resistor when *R* = 0R=0.

We get by normalizing the actual powers in the various resistors to this ideal power,

The last equation shows the missing term from the equation above. It is simply the power burnt in the parasitic resistor *R*R compared with the power burnt in one termination resistor in an ideal situation. The rest of the terms correspond to the power burnt in the load resistor and the power burnt in the source resistor by the return wave.

When the interconnection is resistive it will burn power, so the sum of the square of *S*_{11} and *S*_{21} is less than one.

What about the partly inductive interface in Figure 5.8?

Figure 5.8 An inductor in series with the source impedance.

Here

This energy that goes into the output load is simply the outgoing wave.

At the input we see the driving impedance as *R*_{t}Rt ohms with a load that looks nonideal. With an inductive nonideality we see

We identify again the first terms as the incoming wave and the last term as the returned amplitude.

We can now identify the various S-parameters:

We see now

We can also calculate *S*_{21} for the system with a shunting capacitor. We find

We can now infer that in a purely reactive environment, the sum of the square of the S-parameters is 1; there is no power lost in the medium. The formal proof is beyond the scope of this book.

If the interconnect is purely reactive, the sum of the square of *S*_{11} and *S*_{21} is equal to one; there is no power burnt in the interconnection.

For the previous two examples it is obvious that *S*_{12} = *S*_{21} due to symmetry. But this is in fact generally true for reciprocal systems (no active devices, ferrites, or plasmas) (see [2]).

Finally, we wrap up this section with an example of how to estimate insertion loss (*S*_{21}) for a resistive transmission line. Imagine the following situation depicted in Figure 5.9:

Figure 5.9 Geometry of a single ended transmission line.

We have a transmission line characterized at high frequencies where the skin depth is smaller than the conductor dimensions. It runs over a perfect ground plane (we will generalize this later to a real ground plane).

##### Simplify

We know that the current will run in the bottom of the conductor to minimize the magnetic field, and we know the width of the wire and the skin depth. In Figure 5.10 we have, assuming the dielectric extends beyond the conductor strip,

Figure 5.10 A cross-sectional view of the single transmission line.

So

The width of the skin depth in the ground plane is

*W*

_{gnd}=

*W*+ 2

*h*.

Where we have approximated the extension beyond the edge with a generalization of our findings in section “Currents Induced in Perfectly Conducting Ground Plane” in Chapter 4. At first, we will ignore the resistance of the ground plane for simplicity. It will be simple to generalize later.

##### Solve

We now need to calculate the line impedance with the characteristic impedance from (5.3) and a termination impedance *Z*_{L} = *R*_{t}ZL=Rt. We get from (5.4)

We will first look at this from the small electrical length perspective where *γx*γx is small.

We now get by using equation (5.3) for

which is a fairly intuitive result.

We see then from equation (5.7) that

##### Verify

The transmission line was modeled as a fixed length ≪*λ*/4≪λ/4 to avoid distributed effects in line with our previous modeling assumptions. The excitations were modeled as wave ports. From Figure 5.11 we see field solver shows excellent agreement with our theory up to *Rx*/*R*_{t} ≈ 0.1Rx/Rt≈0.1. After this point there are higher-order effects that start to become important, but we are still within 0.5 dB at *Rx*/*R*_{t} = 0.5Rx/Rt=0.5.

Figure 5.11 A comparison of simulated vs estimation of the loss in a single transmission line.

##### Evaluate

The S-parameters can be understood from a simple local picture through the use of generalized S-parameters and power (voltage) waves. Depending on the situation, a number simple scaling laws are easy to derive and confirm.

##### Summary

There are a couple of convenient microwave theorems useful to keep in mind for passive systems. If the passive system has no resistance, we must have

In particular for a two-port system:

something we just exemplified.

Another convenient nugget is for a reciprocal system

*S*

_{ij}=

*S*

_{ji}

and for a two-port system

*S*

_{21}=

*S*

_{12}.

#### S-Parameters for Long Transmission Lines

In the previous section we looked at a short transmission line where the length was much less than a wavelength. Here we will discuss the more general case of arbitrary length t-lines and the resulting S-parameters. This section will tie together a few of the things we discussed earlier in the chapter.

We have the following situation depicted in Figure 5.12.

Figure 5.12 Pic of t-line in series with termination resistor.

##### Simplify

We will assume the resistance per unit length, *R* ≪ *ωL*R≪ωL. We then have for

and

*Z*

_{L}=

*R*

_{t},

where

##### Solve

We know from (5.4) that the impedance looking into the transmission line from the source port is

Following the *S*_{11} discussion earlier, we have the voltage at the t-line input is

where we have defined an “incoming” and an “outgoing” wave. We find

This expression can be found in most textbooks. Plugging in the numbers we now find