## Abstract

The estimation analysis method is described in the context of sophisticated amplifiers. The purpose is to convince the reader of the usefulness of the technique by whetting their appetite with more complex systems. We start with a simple five transistor circuit and move on to comparators and cascaded amplifiers. All these are studied by applying simplifying assumptions followed by analytical solutions. Noise analysis and appropriate scaling techniques are also described in detail. The chapter further contains design examples and exercises to familiarize the reader more deeply with the methodology.

### 3.1 Introduction

We will discuss somewhat more complex amplifier configurations in this chapter. Following the treatment in Chapter 2 we will here analyze the amplifiers following the estimation analysis method. The calculations will be very similar to the standard literature in, for example, [1–3] and they serve more to showcase the methodology in a familiar setting than to demonstrate any new insights.

We start with the well-known five transistor amplifier, a classic interview question, and continue with cascode stage amplification using feedback. This is followed by a comparator discussion where we put the emphasis on simple timescales and noise analysis. After that, we investigate cascaded stages and the implication in terms of gain, noise, and linearity. Finally we show a couple of design examples that will be used in later chapters where several full-blown design examples will be built and the building blocks we have developed with simple models will be of help in designing the final circuits.

### 3.2 Five Transistor Amplifier

The classic five transistor amplifier is shown in Figure 3.1. It is used all over the circuit world in all manners of applications. We will here focus on noise transfer but we start with a quick description of its operation.

Figure 3.1 Five transistor operational amplifier.

#### Simplify

First we will simplify by assuming the various transistors have the same combination of *g*_{m}, *r*_{o}gm,ro. Then we assume the current bias tail transistor has zero output conductance. The amplifier output resistance is modelled as a resistor *r*_{o} = *r*_{o, p}//*r*_{o, n}ro=ro,p//ro,n between the output node and supply.

#### Solve

The basic operation of the amplifier is as follows: The transconductance gain of the differential pair is causing a current to go into the load. The load is a simple current mirror and the current from transistor *M*_{1}M1 is appearing at the output out-of-phase with the corresponding current generated by transistor *M*_{2}M2. The output voltage swing is finally given by the output current times the load, *r*_{o}ro. We find using *v*_{in} = *v*_{p} − *v*_{n}vin=vp−vn

and the gain

#### Verify

This is a classic calculation that can be found in [3] for example. Let us now look at noise transfer. This is a common interview question.

**Simplify**

The noise from all the transistors is uncorrelated so the noise powers will add

The noise voltage is small so a linearized version of the circuit suffices to capture the noise transfer function.

The NMOS transistors have the same transconductance,

*g*_{m, n}gm,n and PMOS has*g*_{m, p}gm,p

#### Solve

We will solve this by calculating the noise transfer from each of the noise sources and add their power at the output.

Calculating KCL at both the source and the drain shows half the noise current goes through the opposite transistors source node into the PMOS mirror, the other half goes through the same transistor and closes on itself, see the zoomed-in portion of Figure 3.1. The loop formed by the noise current that goes through the opposite transistor causes the current to be mirrored by the PMOS load and the two half currents add up at the output node. We find

The PMOS current mirroring is much simpler, we have from the section “Current Mirror” in Chapter 2 ipout2=2⋅4kTγgm,p.

Finally, the current bias transistors current splits into two where one half goes through the PMOS mirrors the other directly to the output load resistor. Keeping track of the sign of the current we find

The total output noise voltage now becomes

And input-referred,

where we have assumed the correction factor *γ*γ, is the same for both NMOS/PMOS.

#### Evaluate

The final expression here looks deceptively simple. The key realization here is the noise currents for the differential pair transistors actually splits evenly and gets transferred to the output through two different paths.

### 3.3 Cascode Stage Amplification Using Active Feedback

In Chapter 2 we saw how a cascode transistor improved the output impedance of a current mirror. We can go one step further and we will now show an even higher impedance can be achieved with active feedback. Let us look at Figure 3.2. The amplifier senses the cascode source voltage and amplifies it to drive the gate of the cascode transistor. We will next analyze this within the estimation analysis framework we have been using.

Figure 3.2 Cascode stage with an amplifier in feedback.

#### Simplify

Let us simplify by assuming the gain has infinite bandwidth. We leave to the reader to solve the finite bandwidth case.

#### Solve

Similarly to the previous example we have

The only difference to before is the gain *A* + 1A+1 in front of the transconductance. The result is

*Z*

_{o}= (2 + (

*A*+ 1)

*g*

_{m}

*r*

_{o})

*r*

_{o}.

#### Verify

This calculation can be found in [2] for example, where the active cascode case is investigated in detail.

#### Evaluate

As with the previous example we see a great additional impedance boost can be achieved with a cascode transistor, this time using an additional amplifier in a loop configuration.

### 3.4 Comparator Circuit

A comparator circuit is shown in Figure 3.3. This so-called strong-arm comparator is a work horse in modern integrated circuit data converters. It has gained this popularity due to its low-power, a few mW is not unusual, high gain and speed. We will analyze the circuit in a few steps where we will employ the estimation analysis to each. It is expected that with such a popular circuit topology there is plenty of analysis in the literature, see [5, 6], to just mention a few and we will intentionally be somewhat brief in our discussion here.

Figure 3.3 Strong-arm comparator circuit.

#### Comparator Analysis

The analysis can be naturally simplified by dividing it into three phases the circuit goes through as a function of time:

Reset phase. Here transistors

*M*_{7}–*M*_{10}M7–M10, turns on pulling the nodes,*o*_{p}op,*o*_{n}on,*A*A,*B*B to*vdd*. Also the switch,*M*_{0}M0, at the tail turns off the differential pair so the rest of the nodes can be pulled high to*vdd*.

Initialization phase. The reset voltage goes high enabling the differential pair to be active and releasing the rest of nodes

*o*_{p}op,*o*_{n}on,*A*A and*B*B. The nodes*A*,*B*A,B start to get pulled down by the differential pair until first the NMOS transistors,*M*_{3},*M*_{4}M3,M4 turns on and then the output nodes*o*_{p}op,*o*_{n}on, start to get pulled down until the PMOS transistors*M*_{5},*M*_{6}M5,M6 gate voltage goes below its threshold. The nodes*A*,*B*A,B continues down to ground, in effect shorting out the input pair.

Regeneration phase. Here the input pair is disconnected from the circuit operations and the output stage cross-coupled inverters start to decide if the input is high or low.

We will mostly ignore the reset phase here. This is more due to space limitation than to any prejudice against it. We will discuss the last two stages briefly following the steps in the estimation analysis.

##### Initialization Phase

In the initialization phase the nodes start from their reset voltages, *vdd* and moves depending on the input voltages more or less quickly to the point where the top PMOS transistors turn on. Here we will first show a possible way to simplify this stage and capture some of its characteristics. We then solve this simplified model and compare to simulations.

###### Simplify

Let us simplify the operation of this stage by looking at Figure 3.4. We have removed the tail switch and just look at one side of the circuit. We will estimate the timescales to discharge the capacitances at *A*, *o*A,o.

Figure 3.4 Initialization phase of the strong-arm comparator.

###### Solve

The timescale needed to discharge a capacitance can be found from the governing differential equation, and we will show a simple example here. From basic text books we know that for a capacitor with capacitance *C*C its charge

*Q*=

*C U*,

where *U*U is the voltage across the capacitor. Taking the derivative with respect to time gives

where *I*(*t*)It is the current through the capacitor. We can then estimate the timescale, *τ*τ, by approximating *dU*/*dt* ≈ Δ*U*/*τ*dU/dt≈ΔU/τ and find

For our circuit we see that node *A*A gets discharged due to the current going through transistor *M*_{1}M1. Its capacitance, *C*_{A}CA is set by the combined junction capacitance of *M*_{1}M1 and *M*_{3}M3. When the voltage at *A*A reaches *vdd* − *V*_{t}vdd−Vt, transistor *M*_{3}M3 turns on. We find

where *V*_{t}Vt is the threshold voltage of transistor *M*_{3}M3. The current now continues to discharge node *A*A until it reaches ground and will also discharge the output node, *O*O, until node *O*O goes down enough so that the PMOS transistor turns on. Assuming node *A*A is at ground this results in a timescale for the output node to be discharged of

where we assume the threshold voltages for transistors *M*_{3}M3 and *M*_{5}M5 are the same. In this chapter we will only look at various limits and we will assume the relevant timescale for the initialization phase is either (3.1) or (3.2) depending on the situation. See Figure 3.5a and b for a simulation of the initialization phase, where the input nodes are at the same voltage.

Figure 3.5 Simulation of comparator decision sequence where in (a) and (b) various node voltage are displayed. Figure (c) shows the logarithm of the output differential voltage to indicate the regeneration time scale.

##### Regeneration Phase

At this stage the transistors start to look like cross-coupled inverters and we will use the results from the discussion in the section “Cross-Coupled CMOS Inverter” in Chapter 2. We know from this section that the time evolution of the system varies like

*v*

_{o}~

*e*

^{t/τr}

where

The operation can be easily verified as in Figure 3.5c, where the regeneration cycle can be clearly seen.

###### Evaluate

We see from the estimates of timescales that we need to have a large input stage to generate sufficient current and a low capacitive load in order to reduce the time needed to make a decision. With a capacitive load, *C*_{load}Cload, at the output and the regeneration timescale *τ*_{r}τr from (3.3) shows it is directly dependent on the output capacitance. We need to make sure we have enough transconductance, *g*_{m}gm in the cross-coupled pair to drive it. With this output load we get using *C*_{o} = *C*_{load} + 2*C*_{self}Co=Cload+Cself, where the *C*_{self}Cself can be found from equation (2.33).