Simple Model

Imagine an ideal oscillator oscillating at angular frequency, ω_sωs. We can describe this mathematically as

In order to investigate the phase noise of such a system, let us start with the simple case of a single tone phase oscillation with an amplitude A_mAm, and frequency ω_mωm. We get

Solve

This expression can then be expanded using simple trigonometry:

Vs=A(sinωstcosAmsinωmt+cosωstsinAmsinωmt≈Asinωst+cosωtAmsinωmt

Assumption 1 is a reasonable approximation since the final timing jitter is often small compared with a signals period. We can see by looking at the last term that this phase noise tone actually creates two side bands around the main tone:

AcosωstAmsinωmt=12AAmcosωs+ωmt+cosωs−ωmt.

In terms of frequency spectrum we have for positive frequencies

Vsω~Aδω−ωs+12AAmδω−ωs+ωm+δω−ωs−ωm.

Phase noise is defined as the power in a single sideband divided by the power of the main tone. We find here

Pm=1/2AAmA2=12Am2.(7.1)

(Note the units are often quoted as dBc/HzdBc/Hz since we are comparing two powers, but one can argue the units really should be radians²/Hzradians2/Hz.)

We will return to this observation in a little bit. For this discussion we will assume the phase jitter matters at the zero-crossing point of V_sVs where the slope is positive, which will happen approximately at the points in time where sin(ω_st) = 0sinωst=0, and d sin (ω_st)/dt > 0dsinωst/dt>0, using the assumption A_mAm is small (this won’t work for large phase noise). Let us annotate this ideal crossing time as t = t_nt=tn where n is the zero-crossing number. At this point in time cos(ωt) = 1cosωt=1 to first order in ω(t − t_n)ωt−tn and sin(ω_st) = ω_s(t − t_n)sinωst=ωst−tn and we can simplify the expression for V_sVs to be

V_s = A ω (t − t_n) + A A_m sin (ω_m t) + O(ω (t − t_n))².

Vs=Aωt−tn+AAmsinωmt+Oωt−tn2.

The actual zero crossing will happen at:

V_s = A ω (t − t_n) + A A_m sin (ω_m t) = 0

Vs=Aωt−tn+AAmsinωmt=0

or

A ω (t − t_n) =  − A A_m sin (ω_m t)

Aωt−tn=−AAmsinωmt

t−tn=−Amωsinωmt≈−Amωsinωmtn.

where the last step assumes the modulation frequency ω_m ≪ ωωm≪ω, assumption 2 above. This is a reasonable assumption since most of the time the majority of the noise comes from close to the main tone. The zero crossing is adjusted with a sinusoidal term that differs with crossing number, n. If we keep statistics of all these zero crossings we clearly see that this adjustment, or jitter, is just a sinusoid with an rms value of

jt=−Amωsinωmtn=1T∫0TAmωsinωmtn2dt=Am2ω.

If we look at this in terms of the phase noise definition in equation (7.1), we see we can also define

jt=1ω∑Pm=Twosidebandswithpower12Am2=1ω212Am2=Am2ω.

This is simply a consequence of Parseval’s theorem for this simple model, and we will look at the more general case in the next section. Here we can infer:

jt=1ω∫−∞∞Pmdf=1ω2∫0∞Pmdf.

where the last step assumes the phase noise is symmetric around the tone.

A More General Model

We can look at this in a more general way also. Instead of having an explicit tone in the sidebands, we can have a more general time dependency.

We will ignore a(t)at since for oscillators the term is dampened out due to nonlinear, limiting effects. In a linear system  a(t)at will not affect the zero crossings if it is <A. For nonlinear systems where V_sVs also includes higher-order terms, these higher-order terms will cause (A + a(t))A+at to induce phase noise that is dominated by A, called AM–PM noise. We will not consider these systems here. The general assumptions from the introduction lead to the following simplifications:

Simplify

1. 
   

   1. α(t) ≪ 1,     ∀ tαt≪1,∀t

   
   
2. 
   

   2. dαtdt≪ωs,∀t

Solve

We have then

V_s = A sin (ω_st + α(t)) ≈ A  sin (ω_st) + Aα(t) cos (ω_st).

Vs=Asinωst+αt≈Asinωst+Aαtcosωst.

Close to zero crossings, which we define similarly to the previous section where sin(ω_st) ≈ ω_s(t − t_n)sinωst≈ωst−tn and cos(ω_st) ≈ 1cosωst≈1, we get

V_s ≈ A ω_s(t − t_n) + A α(t)

Vs≈Aωst−tn+Aαt(7.2)

αt=αtn+dαtndtt−tn+Ot−tn2.

For V_sVs to be at a zero crossing we find

Aωst−tn+Aαt=0→t−tn=−αtωs=−αtnωs−1ωsdαtndtt−tn≈−αtnωs

where the last step is just assumption 2 above. We can look at the time average (denoted by 〈⋅〉⋅) of the square of this expression

jrms2=t−tn2=αtn2ωs2.

We have

αtn2=12N∑n=−NNαtn2≈12N2π/ωs∫–N2πωsN2πωsαt2dt→∫−∞∞α′t2dt,N→∞

where we define α^′(t)α′t as α(t_n)αtn in units of phase/time. We can finally use Parseval’s theorem and get

αtn2=∫−∞∞α′t2dt=∫−∞∞α̂f2df=Pf=α̂f2=∫−∞∞Pfdf

where α̂f has units radians/Hz and the single sideband noise (SSB) power, P(f)Pf, has units [radians²/Hz]. We then get

jrms=t−tn2=∫−∞∞Pfdfωs2=1ωs∫−∞∞Pfdf=1ωs2∫0∞Pfdf.

Evaluate

There is one particularly interesting thing to note about the derivation. The last term in (7.2) has units of voltage. Let us replace this with a voltage noise term v_n(t)vnt instead, so we find

V_s ≈ A ω_s(t − t_n) + v_n(t).

Vs≈Aωst−tn+vnt.

As before, for this to be at a zero crossing we find

Aωst−tn+vnt=0→t−tn=−vntnAωs

where we have assumed the terms  v_nvn vary slowly compared with the main tone. We get

jrms2=t−tn2=vntn2Aωs2.

With this we see there is no way to distinguish the added voltage noise from the phase noise. We can look at the jitter phenomenon either as a phase noise or as an added voltage noise source. This is the root cause of the somewhat confusing units, as described earlier; we can view this spectrum as either a phase or a voltage for small phase deviations. Likewise, in modern simulators we can choose to calculate jitter from a phase noise integration or by looking at the voltage noise at the zero crossings. The two approaches should obviously agree. Note that this is, strictly speaking, only true when assumption 2 is valid. For large phase deviations we do not have correspondingly large voltage noise. Instead, the voltage noise has a natural limitation referred to as linewidth.

Finally, we note that when using the voltage noise domain approach, the voltage noise source transfers to jitter as

jrms=σ=vnt2Aωs.

The denominator Aω_s = dV_s/dtAωs=dVs/dt. We find

σ=vnt2dVs/dt.(7.3)

This is the well-known “ohm’s” law of jitter [1, 13].

Summary

The jitter–phase noise relationship is a simple calculation of the phase noise power in a sideband divided by the fundamental tone cycle frequency. A simple sinusoidal noise source is helpful when explaining the jitter–phase noise relationship.

DC Specifications

Power consumption: A key DC specification is the power consumption. In modern life, battery powered devices are very popular and keeping the power consumption low for all the circuit components is critical for market success.

AC Specifications

We describe briefly the most common AC specifications for PLLs here.

• 
  

  Loop bandwidth: the closed loop bandwidth is a key to stability considerations. If it is too wide, the phase detector discrete sampling operation will cause problems. Depending on the cleanness of the on-chip VCO vs the reference oscillator, one might choose wide vs narrow bandwidths.

  
  
• 
  

  Phase margin: key to loop filter design and stability.

  
  
• 
  

  Lock time: the time it takes for a PLL to lock.

  
  
• 
  

  Jitter: the accuracy of the resulting clock is important for ADC applications, as will be discussed later in the chapter.

  
  
• 
  

  Spur level: spurs from the reference clock can show up in unexpected places.

Phase Detector

The role of the phase detector is to amplify the phase difference between two input square waves, referred to as the reference clock and the, possibly divided down, oscillator clock. It can be implemented in many different ways, and we will not go into all the possibilities here. Instead, we will take a brief look at a phase frequency detector followed by a charge pump implementation, depicted in Figure 7.2. It is a very common workhorse in the industry.

Figure 7.2 A functional view of a phase detector implemented as a phase frequency detector with a charge pump.

The flip-flops are usually up or down edge sensitive. Depending on which edge comes first, the upper or lower current source is turned towards the output where it sources or sinks charge from the next block, which is the filter block consisting of a capacitor to ground, for simplicity. When the edge from the opposite source comes into the phase detector, the currents are turned off from the output. In this way the difference in phase between the reference and the divided down clock is translated into a current pulse. We can define the gain of this block as

KPD=I+−I−2π−−2π=2Ic4π=Ic2π.

The phase difference can go from +2π+2π to −2π−2π.

The time it will take to bring the PLL all the way from its start-up condition to phase lock is known as the pull-in time. Let us do an order of magnitude estimate of this time using estimation analysis.

Simplify

First we assume the output of the phase detector sits at ground and the VCO is tuned such that the correct output frequency occurs when the control voltage at the input, which is the same as the phase detector output, is at power supply VDD, typically 7–900 mV in small geometry CMOS. The charge pump needs to bring up the output node all the way from ground to VDD. We know from our earlier discussion, on comparator analysis in Chapter 3, that this scales like

Tpull‐in=Δt=CΔUI

The analysis is somewhat complicated by the fact the charge pump is only on for a limited time and it is possible the edge order will switch during the pull-in stage, depending on the overall dynamics. We will ignore such complications here.

Solve

This is now simply a matter of plugging in the numbers, and we find

Tpull‐in=C⋅VDDIc=C⋅ΔωVCOKPD2πKVCO

In the last step we use the initial offset in frequency instead of voltage as a measure of how far one needs to go.

Voltage-Controlled Oscillator

The voltage-controlled oscillator will be discussed in much more detail in Section 7.4. Here we will just define the basic characteristics. The easiest way to change an oscillator’s frequency is to change the effective tank load; in almost all cases this means changing a capacitance, and in most modern CMOS technologies this is natural to transistors. There are often specially constructed varactor devices with this particular property such that their capacitance is changing with its bias voltage. We can now define the gain of a voltage-controlled oscillator as K_VCOKVCO and we find we have an output frequency

with a given input voltage V_inVin; note the unit of K_VCOKVCO is in angular frequency 2πf2πf [MHz/V]. The K_VCOKVCO is assumed to be constant for estimation calculations, but in a real circuitry it will vary with voltage.

For PLL analysis we are interested in phase and not in frequency, which can often be a confusing difference. Let us think of a sine wave

The argument to the sinus function is a phase, but there is a frequency variable in the expression. Phase is defined as the integral of frequency. In our case in our sine wave we have a phase

θ=2π∫0tft′dt′=∫0tωt′dt′=ωt.

In particular, for a time varying frequency this formula can be really helpful. We can now simply relate the input voltage to the oscillator to the output phase as

which in Laplace domain corresponds to a division by ss,

θouts=KVCOsVins.

Frequency Divider

The frequency divider simply takes an input frequency and divides it by the desired factor NN. The corresponding change in phase is simply a division by NN. The gain is now

KDIV=1N.

PLL Filter

We will discuss this block further in section “Fundamental Stability Discussion.” For now, we will simply describe it as a two-port system with transfer function F(s)Fs.

Simplify

We will consider a phase-locked loop as in Figure 7.3. It consists of an input reference signal, a phase detector (PD), a filter, a VCO and a divider circuit. The way to simplify such a system is to linearize all the blocks and assign a gain, or transfer function, to each one. These transfer functions for the various components are illustrated in the figure. Usually, the blocks are described in terms of Laplace transformations. In a typical application one is interested in the phase transfer in the loop, and all entities here refer to phase. The variable ss represents the modulation frequency around the nominal frequency. The linearization technique we describe here is known as the continuous time approximation where we ignore the fact that the phase detector–charge pump combination is actually a discrete time block. For this approximation to be valid, the loop filter bandwidth needs to be about 10× lower than the reference frequency.

Figure 7.3 Basic PLL topology with block gains.

Solve

We start by looking at the error signal,

es=Fin−esFsKVCO/sNKPD

We find explicitly,

es=FinKPD1+FsKVCOKPD/sN

We now find the transfer function T(s) = v_o(s)/F_inTs=vos/Fin from input to the VCO output

Ts=esFsKVCOsFinKPDFsKVCO/s1+FsKVCOKPD/sN=KPDFsKVCOs+FsKVCOKPD/N(7.4)

Verify

This is a well-known calculation and can be found in most textbooks on PLLs.

Evaluate

Depending on the filter, we see we have at least a first-order characteristic equation in the denominator of equation (7.4).

Simplify

For the filter function we will need a low-pass filter, and since the output of the charge pump is a current, the simplest low-pass filter is simply

Fs=1sC

We find then

Ts=vosFin=KPDKVCO/Cs2+KVCOKPD/CN.

Solve

This is a two-pole system and we can find the poles with a bit of rewrite:

KPDKVCO/Cs2+KVCOKPD/CN=1jKVCOKPDN/Cs−jKVCOKPD/CN−KVCOKPDN/Cs+jKVCOKPD/CN.

From Appendix B we see this has the time solution

KVCOKPDNCejKVCOKPD/CNt−e−jKVCOKPD/CNt.

Clearly, while it does not have any increasing amplitude with time, the loop will oscillate. In most definitions of stability this situation is referred to as marginally stable, although in practice it is not acceptable. The oscillation frequency is called the natural frequency

ωn=KVCOKPDCN.

With this definition we find for

Ts=ωn2Ns2+ωn2.

The stability situation is not so good and we need to do something about that, but first let us look at the bandwidth. By replacing s → jωs→jω and looking at the magnitude of T(jω)Tjω, we have

Tjω=ωn2N−ω2+ωn2.

We see there is a singularity at the natural frequency. Let us look beyond that (denominator changes sign) and find the 3 dB bandwidth.

ωn2Nω3dB2−ωn2=N2

ω3dB=ωn1+2.

In this case, the bandwidth is a tad higher than the natural frequency. As a side note, it is interesting that among the real PLLs one can buy in the market, there is often quite a bit of peaking around the natural frequency. We will see shortly that this kind of response is fairly straightforward to correct.

Verify

These are all standard calculations that can be found, for example, in [2, 3].

Evaluate

The expression for the bandwidth is dependent on the filter coefficients.

From a stability viewpoint, the simplification we did here in which we had a simple capacitor as integrator is simply not acceptable. In order to improve the situation we need to add a real part in the left-hand plane to the poles. We will investigate this in the next section.

Improved Stability

The suspicion is now that our loop filter is too trivial. We just have a simple integrator, a capacitor. Let us attempt a more complicated one.

Simplify

Fs=1+assC

where a > 0a>0. For low frequencies we retain our integrator action, but for high frequencies we have added a zero resulting in a constant output.

Solve

Putting this into our original transfer function, we find

Ts=KPDFsKVCOs+FsKVCOKPD/N=ωn21+asNs2+1+asωn2.

Let us solve for the roots

s2+1+asωn2=0

s+aωn222−aωn222+ωn2=0

s=−aωn22±jωn2−aωn222

Since a > 0a>0 we see we have been successful in our quest of creating a pole in the left-hand plane. Furthermore, we see we can get rid of any oscillation by choosing

21ωn=a.

This particular choice is referred to as a critically damped system. Let us put this choice into the transfer function and solve for the time behavior

Ts=ωn2N1+ass+aωn2/22=2ωnNωn/2+ss+ωn2.

We find from an inverse Laplace transform the impulse response is

T(t) = A te^−ω_nt + Be^−ω_nt.

Tt=Ate−ωnt+Be−ωnt.

There is a little bit of peaking and then the exponential roll-off.

This filter is simply a resistor in series with the capacitor. The input is a current and the output a voltage. We get

1sC+R=1sC1+sRC

and

RC=a=21ωn

or

R=1C2ωn.(7.5)

Finally, the bandwidth of the loop can now be estimated as

Tjω=2ωnNωn/2+jωjω+ωn2=T02=N

Tjω2N2=4ωn2ωn2/4+ω2ωn2−ω22+4ω2ωn2=ωn4+4ωn2ω2ωn2+ω22=ωn4+4ωn2ω2ωn4+2ωn2ω2+ω4=12

ωn4+6ωn2ω2−ω4=0

ω2=3ωn2+10ωn4=ωn23+10

ω=ωn3+10.

Summary

We have used estimation analysis to the full in this example and shown that we can derive some admittedly well-known results following the methodology.

Noise Injected after the Filter

Noise injected after the loop filter can be estimated by simply adding in a noise signal as shown in Figure 7.4.

Figure 7.4 Basic PLL topology with noise injected after the filter.

Solve

Any noise injected after the filter will transfer as such:

esFs+nsKVCOsNKPD=−es

Or,

es=−nsKVCOKPD/sN1+FsKVCOKPD/sN

We get at the VCO output

nFos=esFs+nsKVCOs=−nsKVCOKPD/sN1+FsKVCOKPD/sNFs+nsKVCOs=nsKVCOs−KVCOKPDsN+FsKVCOKPDFs+1=nsKVCOs−KVCOKPDsN+FsKVCOKPDFs+sN+FsKVCOKPDsN+FsKVCOKPD=nsKVCOssNsN+FsKVCOKPD=nsKVCONsN+FsKVCOKPD.

Noise at the VCO Output Due to All Sources

Putting it all together, using the results from Exercise 7.1, we find at the VCO input the noise due to all noise sources in this simple model:

nVCO,outputs=KVCOsns1+FsKVCOKPDsN+KVCOsnPDsFs1+FsKVCOKPDsN+nVCOs1+FsKVCOKPDsN+nrefs−ndivsKVCOsKPDFs1+FsKVCOKPDsN.

We can express these noise sources in terms of the PLL loop transfer function from equation (7.4).

nVCO,outputs=TsKPDFsns+TsKdnPDs+nVCOsNN−Ts+nrefs−ndivsNTs.

These noise sources are uncorrelated and the resulting noise power can be written as

nVCO,outputs2=1KPD2Ts2Fs2ns2+1Kd2Ts2nPDs2+nVCOs21−TsN2+Ts2nrefs2N2+Ts2ndivs2N2.

We see clearly the high pass function of the VCO transfer where most of the remaining blocks are low pass in nature.

PLL Specifications

PLL Block Definitions

From the specifications in Table 7.1 it is clear we need a divide ratio of 10. Let us look at the transfer function

vosFin=esFsKVCOsFin=KPDFsKVCO/s1+FsKVCOKPD/sN

We know N = 10N=10. It remains to define K_VCO, CKVCO,C, and K_PDKPD. For the charge pump we will choose a current of I = 1 mAI=1mA and a filter capacitance of C = 1 pFC=1pF. In a small geometry CMOS process we should have no difficulty with a 1 mA output current at 2.5 GHz. It is often better to use a higher charge pump gain than a high VCO gain due to the VCO sensitivity to the noise of the varactor. We can now look at the natural frequency and define the VCO gain.

ωn=KVCOKPDCN≤180MHz

Plugging in the numbers we find

KVCO≤3⋅1016⋅1010−32π⋅10−12=2π⋅3⋅108Hz/V

This is a fairly reasonable number. We cover about 2.5% of the oscillator frequency and can make some adjustments for various center frequency shifts. We will use the K_VCOKVCO we derived here as a key specification for a VCO design later in this chapter. With a series resistor in the loop filter, it now remains to find this resistance, which we do by choosing a critically damped system. We have from equation (7.5)

R=2Cωn=10kohm

With these parameters we find the key parameters illustrated in Table 7.2.

Table 7.2 Parameters for PLL and noise spectrum

Parameter	Value	Units
NN	1010
KPDKPD	1/2π1/2π	mA/rad
KVCOKVCO	600600	MHz/V
nrefnref	00	V
n(s)ns	00	V
nPDnPD	1.2 ⋅ 10−121.2⋅10−12	A/Hz
nVCO(s)nVCOs	1/f1/f	V/Hz
ndivndiv	9 ⋅ 10−109⋅10−10	V/Hz
CC	11	pF
RR	1010	kohm

A close-in phase noise response to the noise sources listed in Table 7.2 is shown in Figure 7.5.

Figure 7.5 Noise sources as a function of frequency offset in PLL. Note, no 1/f noise sources are included.

Simplify

The analysis of a high-performance oscillator begins with an analysis of a damped LC resonator, such as the parallel resonator shown in Figure 7.6.

Figure 7.6 Simple model of VCO tank.

Since there are two reactive components, this is a second-order system, which can exhibit oscillatory behavior if the losses are low or if positive feedback is added. The values are fixed only at a given frequency. All the parameters vary with frequency, where the effective parallel resistance varies the most.

Solve

It is useful to find the system’s response to an external stimulus. We will solve this in two ways and show they are equivalent. First we will discuss a time domain solution, which we will use later. Then we will solve the same problem in the Laplace domain. First, let us look at the circuit in Figure 7.6 and analyze it using KCL:

diRdtRC+iR+iL=0.(7.6)

We also know the inductor’s response to a change in current

LdiLdt=ut=iRR.

We can this use in (7.6)

dudtC+utR+∫0tut′Ldt′=0.

We now define

u˜t=∫0tut′dt′

and we can rewrite

d2u˜tdt2C+du˜tdt1R+u˜tL=0.(7.7)

To solve these types of equation one can of course look up the solution in standard literature, but it is easier to work in the Laplace domain, which we will show shortly.

The general solution to this equation is

ut=Ae−t2RCe+j1LC−14R2C2t+Be−t2RCe−j1LC−14R2C2t

where A, BA,B are integration constants and can be determined from the initial conditions. The Laplace domain version of equation (7.7) becomes, by substituting d/dt → sd/dt→s

s2uC+s1Ru+uL=0

s2C+s1R+1L=0

s+12CR2=14C2R2−1CL