Simple Model

Imagine an ideal oscillator oscillating at angular frequency, ω_sωs. We can describe this mathematically as

In order to investigate the phase noise of such a system, let us start with the simple case of a single tone phase oscillation with an amplitude A_mAm, and frequency ω_mωm. We get

Solve

This expression can then be expanded using simple trigonometry:

Vs=A(sinωstcosAmsinωmt+cosωstsinAmsinωmt≈Asinωst+cosωtAmsinωmt

Assumption 1 is a reasonable approximation since the final timing jitter is often small compared with a signals period. We can see by looking at the last term that this phase noise tone actually creates two side bands around the main tone:

AcosωstAmsinωmt=12AAmcosωs+ωmt+cosωs−ωmt.

In terms of frequency spectrum we have for positive frequencies

Vsω~Aδω−ωs+12AAmδω−ωs+ωm+δω−ωs−ωm.

Phase noise is defined as the power in a single sideband divided by the power of the main tone. We find here

Pm=1/2AAmA2=12Am2.(7.1)

(Note the units are often quoted as dBc/HzdBc/Hz since we are comparing two powers, but one can argue the units really should be radians²/Hzradians2/Hz.)

We will return to this observation in a little bit. For this discussion we will assume the phase jitter matters at the zero-crossing point of V_sVs where the slope is positive, which will happen approximately at the points in time where sin(ω_st) = 0sinωst=0, and d sin (ω_st)/dt > 0dsinωst/dt>0, using the assumption A_mAm is small (this won’t work for large phase noise). Let us annotate this ideal crossing time as t = t_nt=tn where n is the zero-crossing number. At this point in time cos(ωt) = 1cosωt=1 to first order in ω(t − t_n)ωt−tn and sin(ω_st) = ω_s(t − t_n)sinωst=ωst−tn and we can simplify the expression for V_sVs to be

V_s = A ω (t − t_n) + A A_m sin (ω_m t) + O(ω (t − t_n))².

Vs=Aωt−tn+AAmsinωmt+Oωt−tn2.

The actual zero crossing will happen at:

V_s = A ω (t − t_n) + A A_m sin (ω_m t) = 0

Vs=Aωt−tn+AAmsinωmt=0

or

A ω (t − t_n) =  − A A_m sin (ω_m t)

Aωt−tn=−AAmsinωmt

t−tn=−Amωsinωmt≈−Amωsinωmtn.

where the last step assumes the modulation frequency ω_m ≪ ωωm≪ω, assumption 2 above. This is a reasonable assumption since most of the time the majority of the noise comes from close to the main tone. The zero crossing is adjusted with a sinusoidal term that differs with crossing number, n. If we keep statistics of all these zero crossings we clearly see that this adjustment, or jitter, is just a sinusoid with an rms value of

jt=−Amωsinωmtn=1T∫0TAmωsinωmtn2dt=Am2ω.

If we look at this in terms of the phase noise definition in equation (7.1), we see we can also define

jt=1ω∑Pm=Twosidebandswithpower12Am2=1ω212Am2=Am2ω.

This is simply a consequence of Parseval’s theorem for this simple model, and we will look at the more general case in the next section. Here we can infer:

jt=1ω∫−∞∞Pmdf=1ω2∫0∞Pmdf.

where the last step assumes the phase noise is symmetric around the tone.

A More General Model

We can look at this in a more general way also. Instead of having an explicit tone in the sidebands, we can have a more general time dependency.

We will ignore a(t)at since for oscillators the term is dampened out due to nonlinear, limiting effects. In a linear system  a(t)at will not affect the zero crossings if it is <A. For nonlinear systems where V_sVs also includes higher-order terms, these higher-order terms will cause (A + a(t))A+at to induce phase noise that is dominated by A, called AM–PM noise. We will not consider these systems here. The general assumptions from the introduction lead to the following simplifications:

Simplify

1. 
   

   1. α(t) ≪ 1,     ∀ tαt≪1,∀t

   
   
2. 
   

   2. dαtdt≪ωs,∀t

Solve

We have then

V_s = A sin (ω_st + α(t)) ≈ A  sin (ω_st) + Aα(t) cos (ω_st).

Vs=Asinωst+αt≈Asinωst+Aαtcosωst.

Close to zero crossings, which we define similarly to the previous section where sin(ω_st) ≈ ω_s(t − t_n)sinωst≈ωst−tn and cos(ω_st) ≈ 1cosωst≈1, we get

V_s ≈ A ω_s(t − t_n) + A α(t)

Vs≈Aωst−tn+Aαt(7.2)

αt=αtn+dαtndtt−tn+Ot−tn2.

For V_sVs to be at a zero crossing we find

Aωst−tn+Aαt=0→t−tn=−αtωs=−αtnωs−1ωsdαtndtt−tn≈−αtnωs

where the last step is just assumption 2 above. We can look at the time average (denoted by 〈⋅〉⋅) of the square of this expression

jrms2=t−tn2=αtn2ωs2.

We have

αtn2=12N∑n=−NNαtn2≈12N2π/ωs∫–N2πωsN2πωsαt2dt→∫−∞∞α′t2dt,N→∞

where we define α^′(t)α′t as α(t_n)αtn in units of phase/time. We can finally use Parseval’s theorem and get

αtn2=∫−∞∞α′t2dt=∫−∞∞α̂f2df=Pf=α̂f2=∫−∞∞Pfdf

where α̂f has units radians/Hz and the single sideband noise (SSB) power, P(f)Pf, has units [radians²/Hz]. We then get

jrms=t−tn2=∫−∞∞Pfdfωs2=1ωs∫−∞∞Pfdf=1ωs2∫0∞Pfdf.

Evaluate

There is one particularly interesting thing to note about the derivation. The last term in (7.2) has units of voltage. Let us replace this with a voltage noise term v_n(t)vnt instead, so we find

V_s ≈ A ω_s(t − t_n) + v_n(t).

Vs≈Aωst−tn+vnt.

As before, for this to be at a zero crossing we find

Aωst−tn+vnt=0→t−tn=−vntnAωs

where we have assumed the terms  v_nvn vary slowly compared with the main tone. We get

jrms2=t−tn2=vntn2Aωs2.

With this we see there is no way to distinguish the added voltage noise from the phase noise. We can look at the jitter phenomenon either as a phase noise or as an added voltage noise source. This is the root cause of the somewhat confusing units, as described earlier; we can view this spectrum as either a phase or a voltage for small phase deviations. Likewise, in modern simulators we can choose to calculate jitter from a phase noise integration or by looking at the voltage noise at the zero crossings. The two approaches should obviously agree. Note that this is, strictly speaking, only true when assumption 2 is valid. For large phase deviations we do not have correspondingly large voltage noise. Instead, the voltage noise has a natural limitation referred to as linewidth.

Finally, we note that when using the voltage noise domain approach, the voltage noise source transfers to jitter as

jrms=σ=vnt2Aωs.

The denominator Aω_s = dV_s/dtAωs=dVs/dt. We find

σ=vnt2dVs/dt.(7.3)

This is the well-known “ohm’s” law of jitter [1, 13].

Summary

The jitter–phase noise relationship is a simple calculation of the phase noise power in a sideband divided by the fundamental tone cycle frequency. A simple sinusoidal noise source is helpful when explaining the jitter–phase noise relationship.

DC Specifications

Power consumption: A key DC specification is the power consumption. In modern life, battery powered devices are very popular and keeping the power consumption low for all the circuit components is critical for market success.

AC Specifications

We describe briefly the most common AC specifications for PLLs here.

• 
  

  Loop bandwidth: the closed loop bandwidth is a key to stability considerations. If it is too wide, the phase detector discrete sampling operation will cause problems. Depending on the cleanness of the on-chip VCO vs the reference oscillator, one might choose wide vs narrow bandwidths.

  
  
• 
  

  Phase margin: key to loop filter design and stability.

  
  
• 
  

  Lock time: the time it takes for a PLL to lock.

  
  
• 
  

  Jitter: the accuracy of the resulting clock is important for ADC applications, as will be discussed later in the chapter.

  
  
• 
  

  Spur level: spurs from the reference clock can show up in unexpected places.

Phase Detector

The role of the phase detector is to amplify the phase difference between two input square waves, referred to as the reference clock and the, possibly divided down, oscillator clock. It can be implemented in many different ways, and we will not go into all the possibilities here. Instead, we will take a brief look at a phase frequency detector followed by a charge pump implementation, depicted in Figure 7.2. It is a very common workhorse in the industry.

Figure 7.2 A functional view of a phase detector implemented as a phase frequency detector with a charge pump.

The flip-flops are usually up or down edge sensitive. Depending on which edge comes first, the upper or lower current source is turned towards the output where it sources or sinks charge from the next block, which is the filter block consisting of a capacitor to ground, for simplicity. When the edge from the opposite source comes into the phase detector, the currents are turned off from the output. In this way the difference in phase between the reference and the divided down clock is translated into a current pulse. We can define the gain of this block as

KPD=I+−I−2π−−2π=2Ic4π=Ic2π.

The phase difference can go from +2π+2π to −2π−2π.

The time it will take to bring the PLL all the way from its start-up condition to phase lock is known as the pull-in time. Let us do an order of magnitude estimate of this time using estimation analysis.

Simplify

First we assume the output of the phase detector sits at ground and the VCO is tuned such that the correct output frequency occurs when the control voltage at the input, which is the same as the phase detector output, is at power supply VDD, typically 7–900 mV in small geometry CMOS. The charge pump needs to bring up the output node all the way from ground to VDD. We know from our earlier discussion, on comparator analysis in Chapter 3, that this scales like

Tpull‐in=Δt=CΔUI

The analysis is somewhat complicated by the fact the charge pump is only on for a limited time and it is possible the edge order will switch during the pull-in stage, depending on the overall dynamics. We will ignore such complications here.

Solve

This is now simply a matter of plugging in the numbers, and we find

Tpull‐in=C⋅VDDIc=C⋅ΔωVCOKPD2πKVCO

In the last step we use the initial offset in frequency instead of voltage as a measure of how far one needs to go.

Voltage-Controlled Oscillator

The voltage-controlled oscillator will be discussed in much more detail in Section 7.4. Here we will just define the basic characteristics. The easiest way to change an oscillator’s frequency is to change the effective tank load; in almost all cases this means changing a capacitance, and in most modern CMOS technologies this is natural to transistors. There are often specially constructed varactor devices with this particular property such that their capacitance is changing with its bias voltage. We can now define the gain of a voltage-controlled oscillator as K_VCOKVCO and we find we have an output frequency

with a given input voltage V_inVin; note the unit of K_VCOKVCO is in angular frequency 2πf2πf [MHz/V]. The K_VCOKVCO is assumed to be constant for estimation calculations, but in a real circuitry it will vary with voltage.

For PLL analysis we are interested in phase and not in frequency, which can often be a confusing difference. Let us think of a sine wave

The argument to the sinus function is a phase, but there is a frequency variable in the expression. Phase is defined as the integral of frequency. In our case in our sine wave we have a phase

θ=2π∫0tft′dt′=∫0tωt′dt′=ωt.

In particular, for a time varying frequency this formula can be really helpful. We can now simply relate the input voltage to the oscillator to the output phase as

which in Laplace domain corresponds to a division by ss,

θouts=KVCOsVins.

Frequency Divider

The frequency divider simply takes an input frequency and divides it by the desired factor NN. The corresponding change in phase is simply a division by NN. The gain is now

KDIV=1N.

PLL Filter

We will discuss this block further in section “Fundamental Stability Discussion.” For now, we will simply describe it as a two-port system with transfer function F(s)Fs.

Simplify

We will consider a phase-locked loop as in Figure 7.3. It consists of an input reference signal, a phase detector (PD), a filter, a VCO and a divider circuit. The way to simplify such a system is to linearize all the blocks and assign a gain, or transfer function, to each one. These transfer functions for the various components are illustrated in the figure. Usually, the blocks are described in terms of Laplace transformations. In a typical application one is interested in the phase transfer in the loop, and all entities here refer to phase. The variable ss represents the modulation frequency around the nominal frequency. The linearization technique we describe here is known as the continuous time approximation where we ignore the fact that the phase detector–charge pump combination is actually a discrete time block. For this approximation to be valid, the loop filter bandwidth needs to be about 10× lower than the reference frequency.

Figure 7.3 Basic PLL topology with block gains.

Solve

We start by looking at the error signal,

es=Fin−esFsKVCO/sNKPD

We find explicitly,

es=FinKPD1+FsKVCOKPD/sN

We now find the transfer function T(s) = v_o(s)/F_inTs=vos/Fin from input to the VCO output

Ts=esFsKVCOsFinKPDFsKVCO/s1+FsKVCOKPD/sN=KPDFsKVCOs+FsKVCOKPD/N(7.4)

Verify

This is a well-known calculation and can be found in most textbooks on PLLs.

Evaluate

Depending on the filter, we see we have at least a first-order characteristic equation in the denominator of equation (7.4).

Simplify

For the filter function we will need a low-pass filter, and since the output of the charge pump is a current, the simplest low-pass filter is simply

Fs=1sC

We find then

Ts=vosFin=KPDKVCO/Cs2+KVCOKPD/CN.

Solve

This is a two-pole system and we can find the poles with a bit of rewrite:

KPDKVCO/Cs2+KVCOKPD/CN=1jKVCOKPDN/Cs−jKVCOKPD/CN−KVCOKPDN/Cs+jKVCOKPD/CN.

From Appendix B we see this has the time solution

KVCOKPDNCejKVCOKPD/CNt−e−jKVCOKPD/CNt.

Clearly, while it does not have any increasing amplitude with time, the loop will oscillate. In most definitions of stability this situation is referred to as marginally stable, although in practice it is not acceptable. The oscillation frequency is called the natural frequency

ωn=KVCOKPDCN.

With this definition we find for

Ts=ωn2Ns2+ωn2.

The stability situation is not so good and we need to do something about that, but first let us look at the bandwidth. By replacing s → jωs→jω and looking at the magnitude of T(jω)Tjω, we have

Tjω=ωn2N−ω2+ωn2.

We see there is a singularity at the natural frequency. Let us look beyond that (denominator changes sign) and find the 3 dB bandwidth.

ωn2Nω3dB2−ωn2=N2

ω3dB=ωn1+2.

In this case, the bandwidth is a tad higher than the natural frequency. As a side note, it is interesting that among the real PLLs one can buy in the market, there is often quite a bit of peaking around the natural frequency. We will see shortly that this kind of response is fairly straightforward to correct.

Verify

These are all standard calculations that can be found, for example, in [2, 3].

Evaluate

The expression for the bandwidth is dependent on the filter coefficients.

From a stability viewpoint, the simplification we did here in which we had a simple capacitor as integrator is simply not acceptable. In order to improve the situation we need to add a real part in the left-hand plane to the poles. We will investigate this in the next section.

Improved Stability

The suspicion is now that our loop filter is too trivial. We just have a simple integrator, a capacitor. Let us attempt a more complicated one.

Simplify

Fs=1+assC

where a > 0a>0. For low frequencies we retain our integrator action, but for high frequencies we have added a zero resulting in a constant output.

Solve

Putting this into our original transfer function, we find

Ts=KPDFsKVCOs+FsKVCOKPD/N=ωn21+asNs2+1+asωn2.

Let us solve for the roots

s2+1+asωn2=0

s+aωn222−aωn222+ωn2=0

s=−aωn22±jωn2−aωn222

Since a > 0a>0 we see we have been successful in our quest of creating a pole in the left-hand plane. Furthermore, we see we can get rid of any oscillation by choosing

21ωn=a.

This particular choice is referred to as a critically damped system. Let us put this choice into the transfer function and solve for the time behavior

Ts=ωn2N1+ass+aωn2/22=2ωnNωn/2+ss+ωn2.

We find from an inverse Laplace transform the impulse response is

T(t) = A te^−ω_nt + Be^−ω_nt.

Tt=Ate−ωnt+Be−ωnt.

There is a little bit of peaking and then the exponential roll-off.

This filter is simply a resistor in series with the capacitor. The input is a current and the output a voltage. We get

1sC+R=1sC1+sRC

and

RC=a=21ωn

or

R=1C2ωn.(7.5)

Finally, the bandwidth of the loop can now be estimated as

Tjω=2ωnNωn/2+jωjω+ωn2=T02=N

Tjω2N2=4ωn2ωn2/4+ω2ωn2−ω22+4ω2ωn2=ωn4+4ωn2ω2ωn2+ω22=ωn4+4ωn2ω2ωn4+2ωn2ω2+ω4=12

ωn4+6ωn2ω2−ω4=0

ω2=3ωn2+10ωn4=ωn23+10

ω=ωn3+10.

Summary

We have used estimation analysis to the full in this example and shown that we can derive some admittedly well-known results following the methodology.

Noise Injected after the Filter

Noise injected after the loop filter can be estimated by simply adding in a noise signal as shown in Figure 7.4.

Figure 7.4 Basic PLL topology with noise injected after the filter.

Solve

Any noise injected after the filter will transfer as such:

esFs+nsKVCOsNKPD=−es

Or,

es=−nsKVCOKPD/sN1+FsKVCOKPD/sN

We get at the VCO output

nFos=esFs+nsKVCOs=−nsKVCOKPD/sN1+FsKVCOKPD/sNFs+nsKVCOs=nsKVCOs−KVCOKPDsN+FsKVCOKPDFs+1=nsKVCOs−KVCOKPDsN+FsKVCOKPDFs+sN+FsKVCOKPDsN+FsKVCOKPD=nsKVCOssNsN+FsKVCOKPD=nsKVCONsN+FsKVCOKPD.

Noise at the VCO Output Due to All Sources

Putting it all together, using the results from Exercise 7.1, we find at the VCO input the noise due to all noise sources in this simple model:

nVCO,outputs=KVCOsns1+FsKVCOKPDsN+KVCOsnPDsFs1+FsKVCOKPDsN+nVCOs1+FsKVCOKPDsN+nrefs−ndivsKVCOsKPDFs1+FsKVCOKPDsN.

We can express these noise sources in terms of the PLL loop transfer function from equation (7.4).

nVCO,outputs=TsKPDFsns+TsKdnPDs+nVCOsNN−Ts+nrefs−ndivsNTs.

These noise sources are uncorrelated and the resulting noise power can be written as

nVCO,outputs2=1KPD2Ts2Fs2ns2+1Kd2Ts2nPDs2+nVCOs21−TsN2+Ts2nrefs2N2+Ts2ndivs2N2.

We see clearly the high pass function of the VCO transfer where most of the remaining blocks are low pass in nature.

PLL Specifications

PLL Block Definitions

From the specifications in Table 7.1 it is clear we need a divide ratio of 10. Let us look at the transfer function

vosFin=esFsKVCOsFin=KPDFsKVCO/s1+FsKVCOKPD/sN

We know N = 10N=10. It remains to define K_VCO, CKVCO,C, and K_PDKPD. For the charge pump we will choose a current of I = 1 mAI=1mA and a filter capacitance of C = 1 pFC=1pF. In a small geometry CMOS process we should have no difficulty with a 1 mA output current at 2.5 GHz. It is often better to use a higher charge pump gain than a high VCO gain due to the VCO sensitivity to the noise of the varactor. We can now look at the natural frequency and define the VCO gain.

ωn=KVCOKPDCN≤180MHz

Plugging in the numbers we find

KVCO≤3⋅1016⋅1010−32π⋅10−12=2π⋅3⋅108Hz/V

This is a fairly reasonable number. We cover about 2.5% of the oscillator frequency and can make some adjustments for various center frequency shifts. We will use the K_VCOKVCO we derived here as a key specification for a VCO design later in this chapter. With a series resistor in the loop filter, it now remains to find this resistance, which we do by choosing a critically damped system. We have from equation (7.5)

R=2Cωn=10kohm

With these parameters we find the key parameters illustrated in Table 7.2.

Table 7.2 Parameters for PLL and noise spectrum

Parameter	Value	Units
NN	1010
KPDKPD	1/2π1/2π	mA/rad
KVCOKVCO	600600	MHz/V
nrefnref	00	V
n(s)ns	00	V
nPDnPD	1.2 ⋅ 10−121.2⋅10−12	A/Hz
nVCO(s)nVCOs	1/f1/f	V/Hz
ndivndiv	9 ⋅ 10−109⋅10−10	V/Hz
CC	11	pF
RR	1010	kohm

A close-in phase noise response to the noise sources listed in Table 7.2 is shown in Figure 7.5.

Figure 7.5 Noise sources as a function of frequency offset in PLL. Note, no 1/f noise sources are included.

Simplify

The analysis of a high-performance oscillator begins with an analysis of a damped LC resonator, such as the parallel resonator shown in Figure 7.6.

Figure 7.6 Simple model of VCO tank.

Since there are two reactive components, this is a second-order system, which can exhibit oscillatory behavior if the losses are low or if positive feedback is added. The values are fixed only at a given frequency. All the parameters vary with frequency, where the effective parallel resistance varies the most.

Solve

It is useful to find the system’s response to an external stimulus. We will solve this in two ways and show they are equivalent. First we will discuss a time domain solution, which we will use later. Then we will solve the same problem in the Laplace domain. First, let us look at the circuit in Figure 7.6 and analyze it using KCL:

diRdtRC+iR+iL=0.(7.6)

We also know the inductor’s response to a change in current

LdiLdt=ut=iRR.

We can this use in (7.6)

dudtC+utR+∫0tut′Ldt′=0.

We now define

u˜t=∫0tut′dt′

and we can rewrite

d2u˜tdt2C+du˜tdt1R+u˜tL=0.(7.7)

To solve these types of equation one can of course look up the solution in standard literature, but it is easier to work in the Laplace domain, which we will show shortly.

The general solution to this equation is

ut=Ae−t2RCe+j1LC−14R2C2t+Be−t2RCe−j1LC−14R2C2t

where A, BA,B are integration constants and can be determined from the initial conditions. The Laplace domain version of equation (7.7) becomes, by substituting d/dt → sd/dt→s

s2uC+s1Ru+uL=0

s2C+s1R+1L=0

s+12CR2=14C2R2−1CL

s=−12RC±j−14C2R2+1CL.

From the solutions we see the system’s response is a sinusoid with exponential decay as we found earlier. In order to maintain oscillation we need to periodically dump energy into this (tank) circuit. This is normally done by some kind of active amplifier, which is often modeled as a negative resistor in parallel with the tank.

Verify

This calculation is commonplace and can be found, for example, in [8].

Simplify

We use as a simplification Figure 7.7. The problem can now be solved per harmonic, and here we will limit ourselves to the first harmonic only. In order to have a finite amplitude, the active circuit needs to be nonlinear to reduce the transconductance for high swing. If it does not, the amount of energy dumped into the tank will keep increasing. We will assume the active circuit current varies as such:

iv=−gmv+gm″v3(7.8)

where both gm,gm″>0. The negative first-order term is necessary to overcome the loss due to the real impedance in the tank, while the positive third-order term is necessary to limit the oscillation. The energy argument above means we need to find the amplitude where the absolute value of the time average admittance of the active circuit equals the time average admittance of the tank circuitry. The equation to solve is

where <>〈〉 denotes time average over one period.

Figure 7.7 Simplified model of oscillator with tank and active (nonlinear) circuit.

Solve

First we need to find the time average of the active admittance

y=yv=0+dydvv=0v+12d2ydv2v2=didvv=0v+d2idv2v=0v+12d3idv3v=0v2=−gm+32gm″v2

where we used i(v)iv from (7.8). Expressing

we have the time averaged admittance

Yactive=1T∫0Tytdt=1T∫0T−gm+32gm″v2dt=1T∫0T−gm+32gm″A2cos2ωtdt

We now use

cos2ωt=1+cos2ωt2

to write

Yactive=−gm+34A2gm″

since ∫0Tcos2ωtdt=0.

Solving for the real total admittance of the oscillator now gives us

−gm+gm″A234+1R=0

or

A=gm−1R4gm″3.(7.9)

Verify

This calculation and similar discussions can be found in [8, 13].

Evaluate

We see from equation (7.9) that the transconductance in the tank needs to be larger than 1/R1/R of the tank, otherwise no oscillation is possible. In addition, the third-order term, gm″>0, needs to be small for the amplitude, AA, to be large, which is precisely what one might expect.

Simplify

We can now use the fact that the effective resistance is infinite due to the cross-coupled transconductor providing an opposite resistance that cancels the loss. We have

d2u˜tdt2C+u˜tL=inδt−τ

Note, dimensionally [q_n] = A sqn=As or ampere-second to work out properly. In other words, it is a charge.

Solve

The easiest way to solve these kinds of equations is to go to the Laplace domain and solve it there. We find

s2U˜s+U˜sLC=qnCe−sτ

This is easily solved

U˜s=qne−sτ/Cs2+1/LC=−qnCLC2je−sτs+j/LC−e−sτs−j/LC

This can be converted back to time domain and we find

u˜t=jqn2LCe−jωt−τ−ejωt−τ,t>τ

For the voltage we now find

ut=jqn2LC–jωe−jωt−τ−jωejωt−τ=qn21Ce−jωt−τ+ejωt−τ=qnCcosωt−τ,t>τ

This is now a small disturbance added to the tank at t > τt>τ. Assume now the main oscillation is

If we now add the disturbance due to the injected current at time t = τt=τ we find

vosc=Asinωt+qnACcosωt−τ

The perturbation term can now be identified with the impulse sensitivity function we were looking for, which can be illustrated with a couple of cases.

Verify

Let us look at specific values of ττ. If τ = 0τ=0 we have a simple sine wave with a zero crossing at t = 0t=0

vosc=Asinωt+qnACcosωt≈Asinωt+qnCA

which follows from a trivial trigonometric expansion. All the injected power goes into phase noise. If instead τ = π/(2ω)τ=π/2ω, we find

vosc=Asinωt+qnACcosωt−π2=Asinωt1+qnAC.

The injected noise is pure amplitude noise. This is all we can expect intuitively. Remember the forced units on q_nqn [A s].

We see the perturbation term is very close to equation (7.10) and we identify

where 0 ≤ x ≤ 2π0≤x≤2π.

Evaluate

In summary, we find for the perturbation and its impact on phase noise with a charge impulse q_nqn as a function of phase

vperturbx=qnACΓx=qnqmaxΓx

where

where q_maxqmax is a normalization constant discussed in [12].

And for the rms value,

Гrms=12(7.11)

For LC oscillators this expression will give us a good estimate of the magnitude of the noise.

VCO Specifications

Table 7.3 shows the specifications for the VCO.

VCO Design

As we have discussed previously, a VCO consists mainly of some kind of resonant element, some kind of loop or a tuned resonant circuit, and an active element that replenishes the loss in this loop or resonant element. We will here use our results from the estimation analysis to:

• 
  

  Get a starting point of the design work from the estimation analysis;

  
  
• 
  

  Use this starting point in the simulator where we optimize the parameters.

This is a circuit example of how to use estimation analysis to speed up the design work. A good understanding of the basic behavior is essential to a good-quality end product. The simulator should not give us any surprises; it should just be used to fine-tune the performance, as we will discuss here.

We will focus on an LC VCO. We have two major design tasks. First we need to design the LC tank. We will draw from Chapter 5 to find an inductor with a specific Q. We will then shunt this with a capacitor from the same chapter to define the overall Q of this resonator at 25 GHz, which is the oscillation frequency. When we know the effective shunt loss resistor, we will be prepared to design the cross-coupled pair with a specific g_mgm to overcome the loss. Generally, if we are using a fast enough process, the major headaches will involve the passive tank circuitry. We also need to isolate the output of the VCO from the load of the circuitry that follows. We will therefore use the CD stage we defined in Chapter 2 at the output. The topology we now have is illustrated in Figure 7.9.

Figure 7.9 Basic VCO topology.

Tank Design

To resonate, we need an inductor shunted by a capacitance. We learned in Chapters 4 and 5 that the inductance is set by the current pattern as it flows in a loop. It is therefore most important to include the full current loop, including the flow through the active circuitry, as shown in Figure 7.10.

Figure 7.10 VCO inductor including active circuitry showing AC current path loop.

Do not just include the coil itself. We have also learned that the resonance frequency is set to be the length of the inductor element, so we will attempt the design by having a single-ended inductor of

This gives a single-ended capacitance of

C=1Lω2=1100⋅10−122π⋅25⋅1092=0.4⋅10−12F

A rather large required capacitance is helpful in that the load on the tank can be included as part of the resonance. What will such an inductor look like? We created such a tank in Example 5.5, but the inductor in the tank was just the coil itself; now we need to include the connections from it to the active circuitry to get the inductance right. We will use a length of L_int = 40 μmLint=40μm, where the distance between these legs is d = 10 μmd=10μm. From equation (4.52) we find the added differential inductance due to the legs is

Ladd=4⋅10−7⋅40⋅10−614+ln102≈29pH

which is overestimated by about 30%, so we are off with the inductance by about 10%. The required capacitance is then 10% lower, or C = 0.36 pFC=0.36pF.

In order to adjust the frequency, a varactor needs to be included in the tank design. This device will change the capacitance and so the resonance frequency as a function of its bias voltage. From the specifications we see we need a gain of 300 MHz/V leading to a shift in frequency of 300 M/25 G = 1.2%300M/25G=1.2% variation, leading to a change in capacitance of 2.4%. The capacitance needs to change by 8.5 fF with one volt change. From the technology we find the varactor needs to have a size of roughly m = 2m=2.

Active Design

We now know the tank specs and can proceed with the active design. As a rule of thumb, the worst case is 1/g_m < R/21/gm<R/2. This is to ensure we have enough margin to start the oscillations and to get a reasonable yield. We know the differential tank resistance R_diffRdiff from Example 5.5, from which we get the single-ended resistance RR and can thus calculate the transconductance needed

gm>21R≈6mmho

With this oscillator design we cannot use the thin-ox transistors due to over voltage stress. We instead use a 1.5 V unit transistor from our fictitious technology. From our tabulated transistor we then get a size of 10 fingers device from Appendix A. This transistor has a transconductance g_m ≈ 6 mmhogm≈6mmho and should be enough to get the oscillation going.

Frequency: With these parameters we see that the capacitance of the active stage can be estimated using the calculation in Exercise 2.5. We find C_{load, act} = C_g + 4 C_d = 21 fFCload,act=Cg+4Cd=21fF. The tank capacitance should then be reduced to C_tank = 339 fFCtank=339fF. With the addition of the varactor, which has a nominal capacitance of 10 fF10fF per unit, we need two plus the load CD stage, which has an input capacitance of 9 fF9fF according to Example 2.1, so the final tank capacitor needed has an estimated size of C_tank = 310 fFCtank=310fF.

• 
  

  Amplitude: We have from equation (7.9) that the amplitude will be close to

  
  
  A=gm−1R4gm″⋅3=5.8⋅10−3−133045⋅10−3⋅3=0.86V
  Notice that the negative resistance due to the “rotated” capacitor at the output of the follower, see Example 2.1, is negligible compared with the negative resistor provided by the cross-coupled pair.
  
  
  
• 
  

  Phase noise: The expressions (7.10) and (7.11) show the phase noise to be expected is

  
  
  ℒΔω=10logГrms2qmax2⋅in2¯/Δf4Δω2
  
  

where

Гrms=12

in2¯Δf=4kTgmγ.

We assume here, and it is easy to verify, that the noise from the load resistor itself is small compared with the transistor noise. This is a single-ended expression. The differential impact on phase noise is 3 dB lower.

Finally, we have the estimated parameters/sizes for the components of the VCO in Table 7.4.

Simulation

After implementing these sizes in the simulator, we find that the capacitance needed is underestimated, and a slightly updated table is shown in Table 7.5.

Table 7.5 Final sizes for VCO after simulation optimization

Device	Parameter	Value
Inductor	Inductance	110 pH
Capacitor	Capacitance	315.6 fF
Varactor	Multiplicity	2
M1, M2, medium thickness	W/L/NF	1 μm/100 nm/10

The main error in the capacitance is that we have assumed a full C_{load, act}Cload,act at all times. In reality the load capacitance will vary over the cycle for all transistors.

After this has been sized, we confirm the operation with a simple simulation in Figures 7.11 and 7.12.

Figure 7.11 Oscillation frequency vs control voltage.

Figure 7.12 Phase noise of oscillator nodes.

From the figures it is clear our correlation is very good for higher offset frequencies. For lower frequencies the 1/f1/f noise of the transistors starts to come into play. Upon closer examination there are a couple of competing effects that cancel each other out. The transistor noise is overestimated, but it is compensated by the fact we do not include the other noise sources in the system, from the varactor and the tank resistance for example. The single-ended amplitude is ~710 mV as compared with our estimate of 860 mV, so we are around 2 dB off there.

Next Steps: The next steps in the development would be to run through all process, voltage, and temperature corners to make sure we meet the specifications everywhere. After that, a full layout including parasitic elements should be done. The size of the capacitor is likely to need some adjustment after the physical design is completed.

Summary: The main take-home point from this design example is to do one’s homework before simulating. A proper estimation analysis gives a great starting point for the simulation phase where, most of the time, we just need to fine-tune the sizing. However, be aware that VCO design is a rich subject with lots of available topologies and the performance criteria we have focused on here are just the very basics. For a thorough analysis of oscillator design, please see [14]. Having cautioned the reader properly on the limits of the analysis, we have demonstrated here that the path to deeper understanding lies along the route we have just taken.

Simplify

To avoid unnecessary details, let us assume we have a data converter that outputs signed integers in the range −2^N − 1 + 1 → 2^N − 1−2N−1+1→2N−1. This will result in 2^N2N output levels. We further assume

1. 
   

   1. The input to this ADC is a sine wave

   
   
   
   

   f_in = A sin ωt,

   fin=Asinωt,
   
   
   
   

   where

   
   
   
   

   A = 2^N − 1

   A=2N−1
   
   
   
   
2. 
   

   2. N ≫ 1N≫1 so that the input signal can be approximated with a straight line in between transitions.

The output of this simple model is now simply

The 0.5 comes from the assumption that the output is the closest integer level to the input signal. We will now see a step function response at the output as in Figure 7.13.

Figure 7.13 Basic ADC functionality.

Clearly the original tone is in there, but there are also other signals present. Let us find those

Figure 7.14 shows this graphically.

Figure 7.14 Close-up of ADC model output vs input at a transition point. The black curve is the input signal and the gray curve is the output signal.

The noise is simply a sawtooth function over the transition time that starts at 0, goes to −0.5 at the midpoint, t = t_n + 1/2t=tn+1/2, where the transition occurs, which adds a 1 to the noise which is then reduced back to 0 at t = t_n + 1t=tn+1. Mathematically we have

fnoise≈∑n−t−tntn+1−tn+1⋅θt−tn+1/2

where we have used the Heaviside function θθ.

Solve

Let us calculate the power in one of these windows

Pnoise,n=∫tntn+1fnoise2dt=2∫tntn+1/2t−tntn+1−tn2dt=t′=t−tn=2∫0Δtn/2t′Δtn2dt′=2t′33Δtn20Δtn/2=112Δtn.

Over a period,  Δt = TΔt=T, we get a total noise

Pnoise=112T.

The power of the sine wave over the same period is simply

Psignal=A22T.

We have then a signal-to-noise ratio of

SNR=TA2/2T/12=6A2=622N−2.

A more familiar form of this is the dB version

SNRdB=10log622N−2=10log6+10log22N−2=10log6+102N−2log2≈7.781+3.012N−2=6.02N+1.76.

Verify

With N bits the quantization noise from an ADC is such that the SNR becomes

This is a well-known formula and can be found in pretty much all textbooks on ADCs. We see again that by making a really simple model of an ADC we can learn something fundamental about their properties.

Evaluate

When we discuss noise of an ADC, it is often dominated by the quantization noise. There is little point in making an ADC completely dominated by thermal noise since we can get similar performance simply by decreasing the resolution, which can lead to a significant reduction in design time (and power!).

Nyquist Criterion

One effect that should be mentioned here is the Nyquist criterion, which states that with a given sampling frequency, f_sfs, the signal needs to be within a bandwidth of f_s/2fs/2. Curiously, this frequency band could be anywhere in the spectrum in principle. If it is within f_s/2fs/2, it is referred to as the first Nyquist band. If it is between f_s/2fs/2 and f_sfs, it is within the second Nyquist band, and so on. We will derive a precise expression for this effect and its cause in section “Voltage Sampling Theory.”

In the rest of the chapter we will assume the signal is sampled with a certain constant sampling period, T_sTs.

To model a uniform sampling window, one traditionally makes an additional assumption to the first two in section “Basic ADC Model.”

1. 
   

   3. This signal is “active,” meaning two consecutive samples have different output words.

This assumption is needed to decouple the concept of noise power from the signal itself. Imagine a DC signal sitting right at the average trigger point. The output would then have no noise. If it sits right at the boundary, it will have maximum noise, 0.5 lest-significant-bit (LSB). The noise is then clearly signal-dependent. In a real system this is unrealistic since real world signals one encounters in practice are quite active. These three criteria are referred to as Bennet’s criteria (see [15]).

At each sampling point we now make the simplifying assumption that the quantization error is uniformly distributed over the range + 0.5 LSB shown in Figure 7.15 (see [15]).

Figure 7.15 Uniform transition probability.

We find for the noise power:

Pnoise=∫−1/21/2PEE2dE=PE=11/2−−1/2=1=∫−1/21/2E2dE=E33−1/21/2=112LSB.

This is in effect the same calculation we did before, but framed a little differently.

SNR Improvement from Averaging with the Simple Model

Imagine we take the original system and sample it twice as fast, after which we average two consecutive outputs. The overall sampling rate has not changed but something interesting has happened. Let us investigate with a simple model.

Simplify

We will look at two consecutive samples, S_i, S_i + 1/2Si,Si+1/2. Each of these can be modeled as

S_i = V_i + n_i

Si=Vi+ni

where V_iVi is the sampled signal and n_ini is the sampled noise. We will simplify by assuming the noise terms are uncorrelated in consecutive samples so their noise power will add up, and furthermore that on average the noise power is the same for all samples.

Solve

We find now after adding the two samples

Si,tot=Si+Si+1/2=Vi+ni+Vi+1/2+ni+1/2=Vi+Vi+1/2+2ni

After averaging we find the signal is

Vi=12Vi+Vi+1/2

and the noise

ni=122ni=12ni

The noise power is half of the original, or 3 dB in logarithmic terms, while the signal has the same power. The SNR has improved by 3 dB!

Verify

This result can be found in many ADC textbooks [15–19].

Evaluate

In general this is a very powerful method to improve SNR if you can handle the speed; each doubling of the sampling rate followed by averaging improves the SNR by half a bit.

SNR_K = SNR₁ K

SNRK=SNR1K

or in dB

SNR_{dB, K} = SNR_{dB, 1} + 3 (K − 1)

SNRdB,K=SNRdB,1+3K−1

where KK is the oversampling factor.

Key Concept

The SNR of an ADC can be improved by oversampling followed by averaging.

DC Specification

• 
  

  Resolution: This is the number of output bit lanes for ADCs. It does not necessarily relate to the accuracy of the converter.

  
  
• 
  

  Integral nonlinearity (INL): This is the deviation of the output code from a straight line drawn through zero and full scale when the input is a straight DC ramp.

  
  
• 
  

  Differential nonlinearity (DNL): This describes the difference between two adjacent code outputs compared with an LSB step size.

  
  
• 
  

  Offset: Matching of components is far from ideal in modern integrated circuits. Mismatch effects will cause offset as referred to the input signal. A zero at the input will result in a nonzero equivalent at the output.

  
  
• 
  

  Power: The power consumption is often a very critical specification when circuitry is used in battery powered devices.

AC Specifications

The AC or dynamic specifications are often the most highlighted ones, given their reputation as being the hardest to meet. This is often the case, but the same weaknesses can usually be found in the DC specifications.

• 
  

  Signal-to-noise ratio (SNR): This is simply the ratio of the signal power to the power of everything else, excluding harmonic distortion.

  
  
• 
  

  Total harmonic distortion (THD): This is the sum of all harmonic powers divided by the power in the main tone, expressed most commonly as a percentage (%). We will use THD in dB.

  
  
• 
  

  Signal-to-noise and distortion ratio (SNDR): This is simply the ratio of the signal power to the power of everything else, including harmonic distortion.

  
  
• 
  

  Effective number of bits (ENOB): The definition of ENOB is somewhat confusing. There is a formal IEEE definition, but most current literature uses a simpler one defined as

  
  
  ENOB=20logSNDR−1.766.02
  
  
  
  
• 
  

  Spurious-free dynamic range: This is the difference in dB between the main tone and the highest spur in the spectrum.

  
  
• 
  

  Bit error rate (BER): This the ratio of conversion errors over the number of conversions done: see Chapter 3.

In most modern papers describing ADC performance the discrete Fourier transform of the output signal is used:

hk=∑n=0N−1Htne−j2πkTtn,tn=nNT,k∈−N2N2−1,Neven

One can use this formula to investigate issues such as SNR, SNDR, THD, and other such issues that occur with reasonable frequency. Things such as 1/f noise, and glitches including missing codes, either require excessive sampling times or need to be investigated with other means. Using these kinds of transforms can be very revealing of the system’s performance. Be on the lookout for odd noise floor behavior, and unusual output signal power. These can be indicative of unhealthy circuit behavior. If the capture time is not long enough, the detrimental effects of jitter can be hidden in the main tone. Apart from some of the rare defects mentioned previously, the Fourier transform of the signal is very revealing of the full circuit behavior.

For our purposes we will use SNR, SNDR, and THD as key specifications to illustrate the use of estimation analysis in the design of data converters.

Simplify

We make the simplification that there are only two time-interleaved data paths. We will first look at the effect of offset differences between the two digitizers followed by a discussion of gain mismatch. We will also assume there is no thermal noise to worry about.

Vo=AsinωnT,2nT≤t≤2n+1TC+AsinωnT,2n+1T≤t<2n+1T.

If we plot this, we find as illustrated in Figure 7.17.

Figure 7.17 Figure showing offset effect. The two dashed curves indicate the offset of the two ADC slices.

Solve

We can now Fourier transform this effect:

Vof=∫−∞∞Vote−jωtdt=∑n,odd∫−∞∞C+AsinωnTe−jωtdt+∑n,even∫−∞∞AsinωnTe−jωtdt=∑n∫−∞∞AsinωnTe−jωtdt+∑n,odd∫−∞∞Ce−jωtdt.

In addition to a sinusoid sampled with a period TT, there is a DC tone sampled with a 2 ⋅ T2⋅T period that will appear at frequencies, m π/Tm/2T, half the sampling frequency. This is simply the up-converted version of the offset in one channel.

The effect of gain mismatch can be analyzed similarly: see Figure 7.18.

Figure 7.18 Figure showing gain mismatch effect. The two dashed curves indicate the gain of each ADC slice.

We now have

Vof=∫−∞∞Vote−jωtdt=∑n,odd∫−∞∞A′sinωsnTe−jωtdt+∑n,even∫−∞∞AsinωsnTe−jωtdt+∑n∫−∞∞AsinωsnTe−jωtdt+∑n,odd∫−∞∞A′−AsinωsnTe−jωtdt.

We have a sinusoid sampled with a period TT and a sinusoid, with amplitude given by the gain mismatch, sampled at half the sampling frequency. This second term will give rise to tones at m π/T ± f_sm/2T±fs.

Verify

These are standard results that can be found, for example, in [19].

Evaluate

In general for an n-interleaved system, any offset will show up as spurs around F_s/nFs/n, and any gain mismatch will show up at F_s/n ± fFs/n±f.

Summary

We have studied simple ADC models and realized some relevant properties by using estimation analysis. Although most of these results are well known, it is hoped that the reader will be encouraged by the methodology used and will be inspired to explore ADCs and their properties on his/her own. By simply pondering the systems under consideration and trying to capture their essence through simple models, much can be learned on one’s own.

ADC Specifications

Table 7.6 shows the specifications for the ADC.

ADC Design

We will use here the results from the estimation analysis we have done with several circuits along the way in this book, in particular from Chapters 2 and 3, to:

• 
  

  Get a starting point of the design work from the estimation analysis

  
  
• 
  

  Use this starting point in the simulator where we optimize the parameters

This is another circuit example of how to use estimation analysis to speed up the design work. A good understanding of the basic behavior is essential to a good-quality end product. The simulator should not give us any surprises; it should just be used to fine-tune the performance, as we will discuss here.

The topology we will use is shown in Figure 7.19. The first block is an anti-aliasing filter that simply ensures the signal coming through to the ADC has the signal limited to the appropriate Nyquist band. This block will not be discussed here at all; instead, we assume the input signal is properly band limited.

Figure 7.19 Basic ADC topology.

We will take the input stage, the follower, from Chapter 2, the buffer and comparator from Chapter 3, and for the sampling switch we will first not use any and then compare the bandwidth to the case where we use an ideal one with a series resistance.

One important issue we have not touched upon when designing the comparator is the kickback phenomenon. The tail reset switch in Figure 3.3 will cause the source voltage of the differential pair to move to ground node vss rapidly. This rapid change in voltage will induce a current through the gate source capacitance of the input transistor and into the driving impedance of the input source.

Ikick=CdVdt→ΔVin=IkickZin

This will induce a voltage that will interfere with the precious input signal and can cause significant problems. A simple scaling argument shows

ΔVin≈10⋅10−150.410⋅10−12100≈0.4⋅10−1V.

One is helped to some degree by the differential operation of the circuitry, but if one needs high precision, it may very well be insufficient.

A preferred way to deal with this is to use a preamplifier to isolate the comparator kickback from the input signal. It will also help with offset, but it will cause additional delays and at times it may be unacceptable. One can also use different, higher power, comparators where the circuit is biased the whole time. Here we will use a preamplifier from Example 3.2. We have the topology as outlined in Figure 7.20.

Figure 7.20 Straight flash ADC topology.

The circuit blocks have already been designed with this system specification in mind, and upon putting everything together and simulating we find the following set of results for different frequencies. Note, for these simulations nothing was changed compared with the earlier circuitry. Everything was designed/estimated with proper driving source/load impedance and so no adjustments were made! The resulting spectrums for two separate input tones are shown in Figure 7.21. The final results are shown in Table 7.7.

Figure 7.21 Output spectrum of flash ADC at 100 MHz and 6 GHz.

Bandwidth Estimation

We define the bandwidth as the response at the output of the bottom resistor in the string. The bandwidth is set by two properties of the system, first the CD stage output driver and then the fact that we do not use a sampling switch here. These two facts will limit our bandwidth. The aperture window for the comparator is really short, a few ps from our discussion in Chapter 3, section “Comparator Analysis,” so it will not impact the bandwidth. The CD stage consists of a string of low-ohmic resistors driving the capacitive input stage of the preamp. There are 63 such RCRC time constants and the accumulated effect is more significant than just 63 ⋅ RC63⋅RC, since the filters are loading each other. Instead, we can employ estimation analysis to get an idea of the bandwidth.

Solve

The estimated bandwidth is simply

fBW,lower=12πRC=12π64⋅0.625+1264⋅12⋅10−15=4.0GHz.

Verify

The simulated answer for the RC network itself is

f_{BW, sim} = 7.9 GHz

fBW,sim=7.9GHz

In the full simulation with active circuitry we find the bandwidth slightly lower due to higher effective capacitance, and we end up with

f_{BW ‐ full, sim} = 7.1 GHz.

fBW‐full,sim=7.1GHz.

Figure 7.22 shows something interesting. First, Figure 7.22a shows the gain response as we have described it here with a 3 dB point at about 7 GHz. Figure 7.22b shows the same simulation with an ideal sampling switch (10 ohm series resistance) at the gate of the input stage transistor. Here the bandwidth has improved dramatically! The reason is that the resistive ladder now has time to settle since the input is being held for roughly half the sampling period. We will not go into the details of real sampling switch implementations here but hope the reader will be inspired to explore on her/his own.

Figure 7.22 Gain transfer function vs input frequency; the frequencies above Nyquist have been measured as the folded down frequencies. The input signal is 1 dB backed off full scale. (a) The gain without an input sampling switch, and (b) the gain response with an ideal input sampling switch in series with a 10 ohm resistor.

Distortion Estimation

The distortion will be dominated by the input CD stage. We have seen in Chapter 2 that with a sufficient load, the distortion of a CD stage will be small. In our case we have a large impedance due to the current sink, about 1 kohm, and from the second and third harmonic terms calculated in Chapter 2, Section 2.2 and Example 2.2 we see that the third harmonic term should be

H3∼−2gm′2+gm″gm,0gm,05ZL3Vin3∼10−5

In other words, it is completely negligible. This was also confirmed by simulating low frequencies <100 MHz. For higher frequencies we see from the plots there are some distortion terms showing up, but they are small and will not degrade SNDR by much in this case.

Noise Estimation

The noise is best estimated at the input to the preamplifier. We know from Example 3.1 that the input noise to the comparator is

vn,rmscomp∼IbVtCO4kTγgm,1=3⋅10−30.35⋅25⋅10−154⋅1.38⋅10−23⋅300⋅20.024≈0.7mV

The preamplifier’s output noise is roughly

vn,rmspre∼4kTgm,pγR2+4kTR12πRCcomp,in≈0.9mV.

These two noise sources are uncorrelated, and knowing that the preamplifier gain is around 2, we find the total noise at the preamplifier input to be

vn,rms=vn,rmspre2+vn,rmscomp22=0.6mV.

We need to compare this voltage to full scale ADC input, which is 800 mVppd or

vs,rms=0.822=0.28V

Finally, the signal-to-thermal-noise ratio is then expected to be

SNR=0.280.6⋅10−3≈53dB

Thermal noise should not be a limiting factor for the performance. We see also from the simulation results that the nonquantization noise is contributing roughly 0.5 dB.

Jitter Impact

We can consider the jitter from the PLL system we designed in Section 7.3. From Figure 7.5 we can estimate a jitter of around 10 fs, but that does not include 1/f contribution at low-frequency offset. Including these sources, the best jitter performance reported in the literature is around 50 fs. Let us assume we can match this number and see what the jitter impact would be on our ADC. At the first Nyquist boundary, we find

SNRjitter=1σω=15⋅10−14⋅36⋅109=0.5⋅103→SNRdB=54dB

which is much smaller than the quantization noise. However, at the third and fourth Nyquist bands we may get into trouble if the signal loss is otherwise contained.

Conclusion

We have taken a brief look at the design of a flash ADC. The reader should be aware that a complete ADC design involves far more details. Criteria such as power, offset correction, layout parasitics, error detection, and many others must also be considered. Still, the exercise serves as an example of what one can do with simple estimation analysis. Other important issues can be addressed in the same way. Of particular interest is that the sizing of the various blocks was not changed in simulation; everything had been set up with the correct load and source impedance, and the sizing we had estimated and sometimes verified earlier was correct. So the circuitry worked! This was, of course, a simple example, but imagine the benefits on a larger scale.

Jitter

The degradation of signal-to-noise ratio due to jitter in the voltage mode was discussed in section “Phase Noise vs Jitter,” where we showed that the equivalent voltage noise follows the well-known jitter “ohms” law (7.3), illustrated in Figure 7.23. We find after some trivial rearrangement that the signal-to-noise ratio of jitter due to voltage sampling is

SNR=Avnt2=Avn,rms=1σω(7.12)

Figure 7.23 Jitter impact on voltage sampling.

Fourier Transforms

In sampling theory we will work with Fourier transforms, and there are a few things worth mentioning before we start. First, we will look at a sampling situation with a fixed sampling period, TT. This means we should define the Fourier transform as

Hf=1T∫−∞∞hte−jωtdt(7.13)

where ω = 2πfω=2πf.

Second, we will work with both positive and negative frequencies. For real-valued functions h(t)ht the following property is easy to prove:

where * denotes the complex conjugate. For practical calculation we will usually study the positive frequencies and simply keep in mind that the negative ones are the complex conjugate of the positive. It is much easier to work with calculations this way.

Third, instead of using functions such as sinωtsinωt one should use Euler’s formula for sinusoidal functions:

From this we see

sinωt=ejωt−e−jωt2j,cosωt=ejωt+e−jωt2(7.15)

Working with e^jωtejωt functions is much easier when calculating Fourier transforms, as should be clear from the definition (7.13).

Working with “negative” frequencies can be a little confusing at first, so let us illustrate how it works with a simple example. Assume we have a function

ft=Asinωst=Asin2πTst

where we need to calculate its power. From the basic definition we find the average power is

P=1Ts∫0Tsf2tdt=A2Ts∫0Tssin2ωstdt=A2Tst2−sin2ωst4ωs0Ts=A2TsTs2=A22

This is all well known. Now let us take the Fourier transform and look at the spectrum

Ff=∫−∞∞fte−jωtdt=∫−∞∞Asinωste−jωtdt=A∫−∞∞ejωst−e−jωst2je−jωtdt=A2j∫−∞∞ejωs−ωt−e−jωs+ωtdt=A2jδωs−ω−δωs+ω(7.16)

where we have used the continuous time definition of the Dirac delta function:

δω=∫−∞∞e−jωtdt

We see here we have two frequency tones at ω =  ± ω_sω=±ωs. Adding their powers, we should end up with the same expression PP above:

Pspectrum=A24+A24=A22=P

To summarize:

1. 
   

   1. When working with negative frequencies, the tones on the negative frequency side are the complex conjugate of their positive frequency counterparts. We can simply stick to integrating the positive frequency power and multiply the result by two.

   
   
2. 
   

   2. Alternatively, if we know the power density for positive frequencies, such as resistor noise, we can extend to negative frequencies by simply dividing the power density by 2 and mirror it along the ω = 0ω=0 axis.

Armed with these ground rules we can start.

Ideal Sampling Switch

For this section we need to know a couple of Fourier transforms that are helpful, as well as a couple of theorems. We start with something with which most readers will be familiar, impulse sampling, and we continue with track and hold and sample and hold sampling.

Simplify

The simple picture we will use throughout the section is pictured in Figure 7.24.

1. 
   

   1. We model a sampling switch as an ideal switch in series with a resistor with zero ohm, R_s = 0Rs=0. The loop is completed by a (sampling) capacitor and a driving voltage source.

   
   
2. 
   

   2. We will also assume for simplicity throughout this section that the on-time is half of the switch period.

Figure 7.24 Showing ideal sampling switch.

Impulse Sampling

Imagine we sample an input sine wave at certain equally spaced points in time only: see Figure 7.25.

Figure 7.25 Impulse sampling.

Mathematically, this can be expressed as multiplying the input with a series of delta functions:

fimpulset=Asinωst∑kδt−kT=∑kAsinωstδt−kT

where TT is the sampling period. As it stands, it is not very informative. We need to take the Fourier transform to learn more, and in order to do this we first need to take the Fourier transform of the sum of delta function so we can use the convolution theorem (see Appendix B). We have

Fδf=∫−∞∞∑kδt−kTe−jωtdt=∑ke−jωkT.

The key observation here is that these terms will be zero unless:

ωkT = n2π    ∀ k.

ωkT=n2π∀k.

The effect of this is a replacement of the sums

∑k=−∞∞e−jωkT→∑n=−∞∞δω−n2πT.

We then find

Fδf=∑n=−∞∞δω−n2πT.

Now we are ready to use the convolution theorem, and we have for

Ffimpulset=FAsinωst∑kδt−kT=∫−∞∞Ff−f′Fδf′df′

∫−∞∞A2iδωs−ω+ω′−δωs+ω−ω′∑n=−∞∞δω′−n2πTdf′=∑n=−∞∞A2iδω−n2πT+ωs−δω−n2πT−ωs.

These delta functions will appear over and over again, so to minimize the clutter we will use the following short forms:

δω,n−ωs=δω−2πnT−ωs

δω,nωs=δω−2πnT+ωs

We then have

Fimpulseω=Ai2∑n=−∞∞δω,nωs−δω,n−ωs.

We have an impulse train with tones of size A/2A/2 around all harmonics of the sampling frequency, as in Figure 7.26. We will see the same kind of calculation again and again all through this section; see [15] for similar discussions.

Figure 7.26 Spectrum of impulse sampling.

Track and Hold Sampling

Track and hold is a sampling technique where the input signal is visible at the output with some periodicity. The rest of the time the signal is held at a sampled value: Figure 7.27 shows an example. We will first discuss the Fourier transform of the track phase. The hold phase is simpler technically and we leave it as an exercise to the reader. The sum of the track and hold phases gives finally the track and hold result. As a bonus we will also present the sample and hold result.

Figure 7.27 A track and hold picture.

Fourier Transform of the Track Phase

The track phase can be viewed mathematically as a multiplication of signal by a square wave with amplitude V = 1V=1. Such a square wave has the Fourier transform:

Fsquareω=∑k=−∞∞Fkδω−2πkT,Fk=e−jπk/212sinπk/2πk/2

The Fourier transform of the track phase

f_track(t) = f_sig(t) f_square(t)

ftrackt=fsigtfsquaret

is now:

Ftrackω=∫−∞∞Ff−f′Fsquaref′df′=∫−∞∞A2jδωs−ω+ω′−δωs+ω−ω′∑n=−∞∞Fnδω′−n2πTdf′=∑n=−∞∞e−jπn/212sinπn/2πn/2A2jδω,n+ωs−δω,n−ωs.

We see here that even integers cancel out (except n = 0n=0). We end up with

Ftrackω=jA4δωs−ω−jA4δωs+ω+A2∑n=odd∞1πnδω,n+ωs−δω,n−ωs.

Fourier Transform of a Track and Hold Signal

We leave the hold phase to the reader as an exercise, and when putting all this together in one formula we get

FT/Hω=Ftrackω+Fholdω=A2je−jωT/4sinTω/4Tω/4∑m=−∞∞δω,mωs−δω,m−ωs+jA4δωs−ω−jA4δωs+ω+A2∑n=odd∞1πnδω,n+ωs−+δω,m+ωs,

and the result can be seen in Figure 7.28.

Figure 7.28 Frequency domain representation of track and hold signal. The track phase is indicated in thick black and the hold phase is given by the dashed line. The track and hold responses are offset slightly from each other to show the response more clearly. The overall sinc function is drawn in thin black.

Fourier Transform of a Sample and Hold Signal

A sample and hold signal where the signal is held constant until the next sample is simply F_hold(ω)Fholdω with the hold period equal to the sampling period. We can simply do the substitution T → 2TT→2T for F_hold(ω)Fholdω in exercise 5 and we end up with

FS/Hω=A2je−jωT/2sinωT/2ωT/2∑m=−∞∞δω,m+ωs−δω,m−ωs.

A picture of the spectrum in shown in Figure 7.29.

Figure 7.29 Frequency domain representation of sample and hold signal. The overall sinc function is drawn in thin black.

Verify

We have studied here some of the basics of sampling and sampled signals. We have seen how, with some basic Fourier series analysis, we can demonstrate a wide range of phenomena. The results presented can be found, for example, in [15].

Evaluate

The sampling effect can be simply estimated via Fourier series.

Noise Sampling

We have been looking at the basic sampling effects from a simple perspective, that of a single tone being subject to ideal sampling. What happens if you sample a circuit with noise? We will consider a refined sampling model where there is a noisy resistor in parallel with a capacitor as in Figure 7.24 with the switch permanently closed.

Lossy Resistor in Parallel with a Capacitor

Let us consider the following situation: a resistor in parallel with a capacitor to ground. The voltage source in Figure 7.24 is v_s = 0vs=0, so the end of the resistor goes to ground and we will study the noise transfer, due to the lossy resistor, of this system to the capacitor when we sample the output node. It is perhaps as simple as one can make it. First, let us study this system without sampling. We can consider a noise voltage sitting in series with the resistor. We find at the capacitor

it=vnt−vtR=Cdvdt..

Since the noise is better known as a spectrum, we will look at the above in frequency space.

v˜n−v˜R=Cjωv˜→v˜=v˜njRCω11+1jRCω=v˜njRCω+1.

The resistor noise is white, and we can now integrate the noise power over frequency to find

∫−∞∞v˜njRCω+12df=v˜n2∫−∞∞1RCω2+1df=v˜n22πRC∫−∞∞1×2+1dx=v˜n22πRCtan−1x−∞∞=v˜n22RC=2kTR2RC=kTC

where we have used

v˜n2=2kTR

v˜n2 is defined over negative frequencies, so the power is half the normal textbook version. This is all well. What happens if we sample this system?

Let us assume at time tt the capacitor has a voltage v(t)vt, the input is

vint=As2jejωst−e−jωst,

and the voltage on the capacitor is governed by a differential equation derived from

Q=CU→dQdt=I=CdUdt.

We find

It=vint−vtR=Cdvtdt

A simple rewrite shows

dvtdt=vint−vtRC=As/2jejωst−e−jωst–vtRC.(7.17)

This is a first-order differential equation that has the solution

vt=Be−tRC−As/2e−jωstRCωs+j+As/2ejωst−RCωs+j=Be−tRC+D−e−jωst+D+ejωst(7.18)

D−=−As/2RCωs+jD+=As/2−RCωs+j.

We take the Fourier of v(t)vt and find, with B = 0B=0 (we assume the initial transient is negligible),

Fvf=∫−∞∞vte−jωtdt=∫−∞∞D−e−jωst+D+ejωste−jωtdt=∫−∞∞D−e−jωs+ωt+D+ejωs−ωtdt=D−δωs+ω+D+δωs−ω.

Ideal Impulse Sampling

Let us sample this with an ideal impulse sampler, where we again use the convolution theorem.

F(v(t)v_s(t)) = F(f) = v(f) ∗ F_δ(f) =  ∫ v(f − f^′)F_δ(f^′)df^′

Fvtvst=Ff=Fvf∗Fδf=∫Fvf−f′Fδf′df′

∫A2−δω−ω′−ωsRCω−ω′−j−δω−ω′+ωsRCω−ω′+j∑δω′−k2πTsdf′=∑k=−∞∞A2δω,k+ωsRCω−k2π/Ts−j−δω,k−ωsRCω−k2π/Ts+j.

This simply means the spectrum with a specific sine wave source is shifted around each sampling frequency harmonic. Imagine now that we integrate ω_sωs over all spectrum, in other words we have a white noise source with noise density A = 2kTRA=2kTR. We find

Vω=kTR∑k=−∞∞1ω+k2π/TsRC−j)−1ω+k2π/TsRC+j)

Vω=kTR∑k=−∞∞2jω+k2π/Ts2R2C2+1).

Figure 7.30 shows that by looking at ω < π/Tω<π/T, the first Nyquist zone, we see that noise contributions from higher harmonics of the sampling clock extend into the first Nyquist zone. We see that even though we restrict ωω to be within the first Nyquist zone, contributions from all harmonics extend into the first Nyquist zone, leaving the total integrated power in the first Nyquist zone equal to the total noise integrated over all frequencies without sampling. In fact, the same can be said about any Nyquist zone. All Nyquist zones contain all noise power in the ideal impulse sampling case. For a sample and hold situation, it is a little bit different, something we will explore next.

Figure 7.30 First three terms of |V(ω)|Vω. Within the first Nyquist zone the noise from the m = +1,2 terms are added to the noise, resulting in an increase in the total noise. The dashed lines indicate harmonics of the sampling frequency and the dash-dotted line the first Nyquist zone.

Finite Pulse Width Sampling

Let us sample this with a square wave where the switch is on for a time T_s/2Ts/2 and the rest of the time the output is zero.

F(v(t)v_s(t)) = F(f) = v(f) ∗ F_square(f) =  ∫ v(f − f^′)F_square(f^′)df^′

Fvtvst=Ff=vf∗Fsquaref=∫vf−f′Fsquaref′df′

∫A2−δω−ω′−ωsRCω−ω′−j−δω−ω′+ωsRCω−ω′+j∑k=−∞∞Fkδω′−2πkTdf′=∑k=−∞∞A2e−iπk/212sinπk/2πk/2δω,k+ωsRCω−k2π/Ts−j−δω,k−ωsRCω−k2π/Ts+j

After integrating the noise source again, we find the following spectrum

Vω=kTR∑k=−∞∞e−iπk/212sinπk/2πk/22jω+k2π/Ts2R2C2+1)

This expression is very similar to what we had before, with the exception of the absence of every even sampling harmonic, except DC.

Verify

This is a much-discussed effect, see for example [20].

Evaluate

With ideal impulse sampling, all Nyquist zones contain all noise power in the unsampled system. Finite sampling width results in a notch filter effect excluding some noise around some harmonics of the sampling frequency.

Key Concept

With ideal impulse sampling, all Nyquist zones contain all noise power in the unsampled system. Finite sampling width results in a notch filter effect excluding some noise around some harmonics of the sampling frequency.

Simplify

Let us consider an ideal charge sampling model starting with the discussion in [21] and Figure 7.31.

Figure 7.31 Ideal current switch.

© [2005] IEEE. Adapted, with permission, from IEEE Trans Circ. Systems.

We will further simplify the discussion by assuming S1 is always on and S2 is an ideal switch that clears the capacitance in no time, with a period T_sTs. When looking at a sine wave, we then have current integration from a time, t_ntn to a time t_n + 1 = t_n + T_stn+1=tn+Ts: see Figure 7.32.

Figure 7.32 Ideal charge sampling in time domain.

Solve

Using

we find the sampled charge

Cn=ATs∫tntn+1sinωtdt=−ATsωcosωttntn+1=ATsωcosωtn−cosωtn+1

where we have defined, A = I₀ ⋅ T_sA=I0⋅Ts, as the charge amplitude. Using

we get:

Cn=ATsωcosωnTs−cosωn+1Ts=ATsω−2⋅sin12ωnTs+ωn+1Tssin12ωnTs−ωn+1Ts=ATsω2⋅sinωnTs+12ωTssin12ωTs≈AsinωnTs,ωTs≪1.(7.20)

We see here that for low frequencies we recover the sampled signal. For higher frequencies there is a roll-off determined by the last sine factor. At Nyquist, ωT_s = πωTs=π this roll-off has an amplitude of A ⋅ 2/ωT_s = A 2/πA⋅2/ωTs=A2/π or −3.9 dB loss compared with DC.

When jitter is added into the picture we get:

where

we get:

Cn=ATsωcosωnTs+σn−cosωn+1Ts+σn+1=ATsωcosωnTscosωσn−sinωnTssinωσn−cosωn+1Tscosωσn+1−sinωn+1Tssinωσn+1.

Assuming,  ωσ_n ≪ 1ωσn≪1, we arrive at

Cn≈ATsωcosωnTs−ωσnsinωnTs−cosωn+1Ts−ωσn+1sinωn+1Ts=ATsωcosωnTs−cosωn+1Ts−ωσnsinωnTs+ωσn+1sinωn+1Ts

For low frequencies ωT_s ≪ 1ωTs≪1 we can now make an interesting observation,

Cn≈AsinωnTs+AsinωnTs+ωTs2σn+1−σnTs+AωcosωnTs+ωTs2σn+1+σn2Cn≈AsinωnTs+AsinωnTs+ωTs2σn+1−σnTs+AωcosωnTs+ωTs2σn+1+σn2(7.21)

The first term is the original signal, while the last two show jitter contributions. Note that if the jitter components are correlated, σ_n + 1 = σ_nσn+1=σn the second term disappears and we have the usual jitter relationship from voltage sampling where the aperture jitter component is proportional to frequency (or the derivative of the signal). One can think of correlated jitter as a low-frequency drift of the sampling point: see Figure 7.33. For anti-correlated jitter σ_n + 1 =  − σ_nσn+1=−σn, the third term disappears and we are left with jitter terms that can be called amplitude jitter in that they peak when signal amplitude peaks, shown in Figure 7.34. For uncorrelated jitter, both the second and third terms will contribute, and for small frequencies the second term is the dominant one. We have jitter effects even at DC.

Figure 7.33 Low-frequency drift of charge sampling points. Correlated sampling points. The distance between the sampling points is correct but the average charge sampling time is off by sigma. This situation typically occurs in low-frequency drifts.

Figure 7.34 Anti-correlated sampling points. The average charge sampling time is correct but the distance between the sampling points is off, causing the slice gain to be off. The odd and even sampling pulse edges move opposite each other.

Another way to think of this is in terms of differential signals. Any charge sampling event can be characterized by either the start or end time of the sampling interval or the common mode time (average) and the differential time. In other words, we can describe the sampling as a correlated signal plus an anti-correlated signal. These two signals can obviously vary with the sampling time.

For general frequencies we can also calculate the response

Cn=ATsωcosωnTs−cosωn+1Ts−ωσnsinωnTs+ωσn+1sinωn+1Ts=ATsω2∗sinωnTs+12ωTssin12ωTs+Jn(7.22)

where

Jn=ATs−σnsinωnTs+σn+1sinωn+1Ts.(7.23)

Verify

These calculations are similar to [21].

Evaluate

We have identified a couple of different modes of operations, and we will discuss them each in turn. We start with the correlated jitter and follow this by the anti-correlated jitter discussion.

Correlated jitter

When the jitter is correlated we get:

Jn,corr=ATsσn(−sinωnTs+sinωn+1Ts=ATsσn2sin12ωTscosωnTs+12ωTs.(7.24)

which is very similar to the main tone except the phase is off by 90 degrees. In other words, it looks like phase jitter. To get the signal-to-noise ratio we need to convert to power and average signal and power over time, TT:

Ncorr=Jn,corr2=1N∑n=1NATsσn2sin12ωTscosωnTs+12ωTs2

If we now define an effective jitter function

σ2=1N∑nσn2cos2ωnTs+12ωTs,N→∞(7.25)

=ATsσ2sin12ωTs2.(7.26)

we see the same roll-off vs frequency as the signal.

For the signal we will also define it similarly

S=Cn2=1N∑n=1NATsω2sinωnTs+12ωTssin12ωTs2=ATsω2sin12ωTs2.(7.27)

We get for

SNcorr=ATsω2sin12ωTs2ATsσ2sin12ωTs2=1σω2.(7.28)

This is same expression one would get for pure voltage sampling; see earlier discussion, equation (7.12). Another way to look at this situation is to see that the sampling instance is off by σ_nσn and if the jitter is slowly changing, the next sample will be off by a similar amount.

Anti-correlated jitter

Let us look at the opposite situation where jitter is anti-correlated, σ_n ≈  − σ_n + 1σn≈−σn+1, and the odd and even sample pulses are moving opposite each other.

Jn,anti‐corr=−ATsσn(sinωnTs+sinωn+1Ts

Jn+1,anti‐corr=−ATsσn+1(sinωn+1Ts+sinωn+2Ts=ATsσn(sinωn+1Ts+sinωn+2Ts.

We see in general that we get a sequence of samples with alternating sign

Jn,anti‐corr=−ATsσn(sinωnTs+sinωn+1Ts=−ATsσn2−1ncos12ωTssinωnTs+12ωTs.(7.29)

For simplicity, let us assume σ_n =  − σ_n + 1 = σσn=−σn+1=σ. We see then that this sequence is generated by multiplying the tone by a square wave with period 2T_s2Ts. The result is a tone at 1/(2 ∗ T_s) − ω/(2π)1/2∗Ts−ω/2π. In other words, the main tone gets no broadening of its profile. This situation is simply one of timing mismatch between odd/even samples, which will create a tone that looks like an interleave gain error around which the jitter noise moved. The cosine term in the previous expression shows that, close to Nyquist, this term is suppressed.

We can now go through the same calculation that led us to the correlated noise power, N_corrNcorr. We find

Nanti‐corr=ATsσ2cos12ωTs2.(7.30)

And

SNanti‐corr=ATsω2sin12ωTs2ATsσ2cos12ωTs2=1σωsin12ωTscos12ωTs2.(7.31)

For low frequencies we see the expected dc value, (T_s/2σ)²Ts/2σ2, while for high frequencies we get ~1/(ω − ω_s)²~1/ω−ωs2, which is a remarkable improvement! The improvement in noise is

Nanti‐corrNcorr=ATsσ2cos12ωTs2ATsσ2sin12ωTs2=cos212ωTssin212ωTs=cot212ωTs.(7.32)

We see this ratio is less than 1 above Nyquist/2.

Uncorrelated jitter

For correlated noise, we get no benefit compared with voltage sampling! For anti-correlated, we get infinite benefit for the tone proper, although the total noise power only rolls down when the main tone is close to Nyquist – still a remarkable improvement in SNR. For uncorrelated jitter, half the jitter will be in the correlated and half will be anti-correlated. We find the total jitter power

Nanti‐corr+Ncorr=ATsσ22cos12ωTs2+ATsσ22sin12ωTs2=ATsσ22cos12ωTs2+ATsσ22sin12ωTs2=ATsσ222=2ATsσ2.(7.33)

As the tone frequency changes, the sum of the contributions from the correlated and anti-correlated portions is the same but their relative power changes. For low frequency the anti-correlated jitter is dominant, while for high frequencies the correlated jitter dominates. This noise power can also be found directly from the expression for J_nJn. We find, noting that both edges contribute equally to noise power,

Nuncorr=Jn,uncorr2=2⋅1N∑n=1NATsσnsinωnTs2=2⋅ATsσ2(7.34)

where we have, similarly to (7.25), defined an effective σσ. And we find

SNuncorr=ATsω2sin12ωTs2ATsσ22=122σω2sin212ωTs=122TsσTsω2sin212ωTs=12Tsσ2sin2xx2,x=12ωTs0≤x≤π2.(7.35)

The improvement for uncorrelated edge noise compared with correlated noise is:

NuncorrNcorr=ATsσ22ATsσ2sin12ωTs2=12sin212ωTs(7.36)

which shows that when (1/2)ωT_s > π/4 → f > 1/4T_s1/2ωTs>π/4→f>1/4Ts we have an improvement of up to 3 dB at Nyquist. Since we still have jitter at DC, there is a penalty for low frequencies compared with correlated noise.

Verify

These two correlation models were simulated with the aid of a Matlab script, and the comparison is shown in Figures 7.35–7.37. We use a simple sinusoidal jitter tone that moves the integration edge up and down in time, similar to the model in section “Phase Noise vs Jitter.”

Figure 7.35 Matlab simulation of correlated charge sampling jitter and comparison with the estimated model.

Figure 7.36 Matlab simulation of anti-correlated sampling jitter and comparison with the estimated model.

Figure 7.37 Matlab simulation of uncorrelated charge sampling jitter and comparison with the estimated model.

Evaluate

The interesting thing to note here is that the anti-correlated signal-to-noise ratio can be significantly higher with the anti-correlated noise at high frequencies. For low frequencies, due to the roll-off of the noise power, it is still better than the correlated noise jitter. This promise caused some excitement early on when it was proposed. However, there is an assumption being made. If we look again at the phase noise response of a typical PLL, in Section 7.1 we found most phase noise was concentrated around the carrier. This causes slow movement of the carrier phase as a function of time. In the context of charge sampling, this means that almost all the jitter is correlated and the SNR degradation due to jitter is more or less identical with voltage sampling. Any portion of the jitter that is uncorrelated will give rise to jitter degradation even for a DC signal. If we can accept the DC degradation, we still need a PLL structure that can spread the noise out so it becomes white or uncorrelated, or we can create a topology that implements an anti-correlated jitter transfer – none of which is obvious, but it is worth some thought.