## Abstract

This chapter describes how to apply estimation analysis to various systems. We start by discussing phase locked loops (PLL) and show how one can model them simply. One of the key properties of PLLs are their jitter performance. A definition of jitter is followed by a way to model the concept using simple noise sources. Next voltage controlled oscillators are described in some detail and various ways to model them using estimation analysis. This is followed by a design example of a VCO where the lessons from the previous chapters are incorporated including design examples. We then proceed to a discussion of analog-to-digital converters, which are described through some simple models. By incorporating design examples from the previous chapters a full straight flash ADC is implemented, where the ADC performance criteria are applied. This is another example of how through estimation analysis one can arrive at a good starting point for fine-tuning of a circuit using a simulator. Sampling methods, such as voltage sampling and charge sampling, are discussed following the estimation analysis method. The chapter concludes with exercises.

In this chapter we will demonstrate how to apply estimation analysis to higher-level systems such as

￮ Feedback systems – PLLs

￮ Fourier transforms and how to efficiently use them when doing estimation analysis – sampling theory

￮ Defining differential equations – circuit analysis

￮ Laplace transforms – loops, both systems and circuits

￮ Simple estimates using nonlinear perturbations – VCO amplitude

￮ Sinusoidal perturbations of large signals – jitter–phase noise relationship

We assume the reader has encountered the basic mathematical theory covering the definitions of these concepts before in elementary classes. The reader does not need a background in the high-level systems themselves, as the discussion will be held at an introductory level.

### 7.1 Introduction

In the previous chapters we have seen a few different examples of the kind of estimation techniques that are helpful in building understanding of physical systems. In particular, the RF sections showed that a two-dimensional approximation, sometimes with additional symmetries, is of great help. There we also dug fairly deeply into certain aspects in order to more easily estimate effects such as inductance and capacitance. The character of this chapter is different. Here we will look into several physical systems where the basic approximations will be different from each other, and we will not dig into issues as deeply as we did earlier. We will paint the picture in broad strokes, with the occasional detailed analysis of systems that sometimes cause confusion to the early career engineer. Common to all analysis is a firm adherence to the belief that detailed mathematical analysis is a key to understanding systems behavior. We also show that analysis does not need to be overbearing and overly tedious. Instead, keeping the models as simple as possible without oversimplifying is the key to success. The overarching theme of the chapter is timing jitter – how it is generated, how it degrades performance, and how it can be countered.

Throughout the chapter we emphasize how to build simple yet relevant models and illustrate several different mathematical techniques. Sometimes the approximations are more or less obvious or familiar, at other times less so. We also include some well-known examples of this type of modeling from the literature to further strengthen our argument that it is both a useful and universal technique to gain understanding.

The chapter discusses phase-locked loops (PLLs) and analog-to-digital converters (ADCs). If one understands these two concepts, in effect loops and time sampling techniques, one can cover a lot of ground in the engineering space. The reader is not assumed to have any prior knowledge of either of these systems and the discussion will be kept at an introductory level for the most part. At the end of the two sections we will discuss specific design examples of certain components of the systems. We start with a discussion of clock generation in the form of PLLs and highlight the jitter aspects. Specifically we will dig into voltage-controlled oscillators (VCOs) in some detail. This is followed by a discussion of ADCs, where we design a flash-type ADC, and in particular sampling theory, where the impact of jitter and other degradations of the signal-to-noise ratio (SNR) are presented in both voltage sampling and charge sampling contexts.

### 7.2 Jitter and Phase Noise

#### Jitter

Since we will encounter the concept of jitter quite a few times in this chapter, let us first define it. Jitter is simply the deviation in time of a clock or data edge from its ideal position. In the literature one finds there are several different types of jitter discussed [1]. It is commonly divided into random jitter (RJ) and deterministic jitter (DJ). Random jitter is Gaussian in nature, with unbounded amplitude, while deterministic jitter is bounded in amplitude. The major jitter components can be further subdivided.

## Deterministic Jitter

## Random Jitter

In this chapter our focus will be on Gaussian jitter.

#### Phase Noise vs Jitter

This section will explore the relationship between phase noise and jitter in two different ways. In the first section we will use a simple model to get a feel for the behavior, and then we will use a more general model in the second section. In both sections we will make two simplifying assumptions, which are not strictly speaking necessary for the argument to hold but for most cases of interest they are relevant. We will assume:

1. The amplitude of the phase change is small compared with a full rotation.

2. The rate of change of the phase is small compared with the main tone.

We will quantify these assumptions in the discussion.

##### Simple Model

Imagine an ideal oscillator oscillating at angular frequency, *ω*_{s}ωs. We can describe this mathematically as

*V*

_{s, ideal}=

*A*sin

*ω*

_{s}

*t*.

In order to investigate the phase noise of such a system, let us start with the simple case of a single tone phase oscillation with an amplitude *A*_{m}Am, and frequency *ω*_{m}ωm. We get

*V*

_{s}=

*A*sin (

*ω*

_{s}

*t*+

*A*

_{m}sin (

*ω*

_{m}

*t*))

###### Simplify

The simplifying assumptions above mean here

1.

*A*_{m}≪ 1Am≪1

2.

*ω*_{m}≪*ω*_{s}ωm≪ωs

###### Solve

This expression can then be expanded using simple trigonometry:

Assumption 1 is a reasonable approximation since the final timing jitter is often small compared with a signals period. We can see by looking at the last term that this phase noise tone actually creates two side bands around the main tone:

In terms of frequency spectrum we have for positive frequencies

Phase noise is defined as the power in a single sideband divided by the power of the main tone. We find here

(Note the units are often quoted as dBc/HzdBc/Hz since we are comparing two powers, but one can argue the units really should be radians^{2}/Hzradians2/Hz.)

We will return to this observation in a little bit. For this discussion we will assume the phase jitter matters at the zero-crossing point of *V*_{s}Vs where the slope is positive, which will happen approximately at the points in time where sin(*ω*_{s}*t*) = 0sinωst=0, and *d* sin (*ω*_{s}*t*)/*dt* > 0dsinωst/dt>0, using the assumption *A*_{m}Am is small (this won’t work for large phase noise). Let us annotate this ideal crossing time as *t* = *t*_{n}t=tn where n is the zero-crossing number. At this point in time cos(*ωt*) = 1cosωt=1 to first order in *ω*(*t* − *t*_{n})ωt−tn and sin(*ω*_{s}*t*) = *ω*_{s}(*t* − *t*_{n})sinωst=ωst−tn and we can simplify the expression for *V*_{s}Vs to be

*V*

_{s}=

*A ω*(

*t*−

*t*

_{n}) +

*A A*

_{m}sin (

*ω*

_{m}

*t*) +

*O*(

*ω*(

*t*−

*t*

_{n}))

^{2}.

The actual zero crossing will happen at:

*V*

_{s}=

*A ω*(

*t*−

*t*

_{n}) +

*A A*

_{m}sin (

*ω*

_{m}

*t*) = 0

or

*A ω*(

*t*−

*t*

_{n}) = −

*A A*

_{m}sin (

*ω*

_{m}

*t*)

where the last step assumes the modulation frequency *ω*_{m} ≪ *ω*ωm≪ω, assumption 2 above. This is a reasonable assumption since most of the time the majority of the noise comes from close to the main tone. The zero crossing is adjusted with a sinusoidal term that differs with crossing number, *n*. If we keep statistics of all these zero crossings we clearly see that this adjustment, or jitter, is just a sinusoid with an rms value of

If we look at this in terms of the phase noise definition in equation (7.1), we see we can also define

This is simply a consequence of Parseval’s theorem for this simple model, and we will look at the more general case in the next section. Here we can infer:

where the last step assumes the phase noise is symmetric around the tone.

##### A More General Model

We can look at this in a more general way also. Instead of having an explicit tone in the sidebands, we can have a more general time dependency.

*V*

_{s}= (

*A*+

*a*(

*t*)) sin (

*ω*

_{s}

*t*+

*α*(t)).

We will ignore *a*(*t*)at since for oscillators the term is dampened out due to nonlinear, limiting effects. In a linear system *a*(*t*)at will not affect the zero crossings if it is <*A*. For nonlinear systems where *V*_{s}Vs also includes higher-order terms, these higher-order terms will cause (*A* + *a*(*t*))A+at to induce phase noise that is dominated by *A*, called AM–PM noise. We will not consider these systems here. The general assumptions from the introduction lead to the following simplifications:

**Simplify**

1.

*α*(*t*) ≪ 1, ∀ tαt≪1,∀t

2. dαtdt≪ωs,∀t

###### Solve

We have then

*V*

_{s}=

*A*sin (

*ω*

_{s}

*t*+

*α*(

*t*)) ≈

*A*sin (

*ω*

_{s}

*t*) +

*Aα*(

*t*) cos (

*ω*

_{s}

*t*).

Close to zero crossings, which we define similarly to the previous section where sin(*ω*_{s}*t*) ≈ *ω*_{s}(*t* − *t*_{n})sinωst≈ωst−tn and cos(*ω*_{s}*t*) ≈ 1cosωst≈1, we get

*V*

_{s}≈

*A ω*

_{s}(

*t*−

*t*

_{n}) +

*A α*(

*t*)

For *V*_{s}Vs to be at a zero crossing we find

where the last step is just assumption 2 above. We can look at the time average (denoted by 〈⋅〉⋅) of the square of this expression

We have

where we define *α*^{′}(*t*)α′t as *α*(*t*_{n})αtn in units of phase/time. We can finally use Parseval’s theorem and get

where α̂f has units radians/Hz and the single sideband noise (SSB) power, *P*(*f*)Pf, has units [radians^{2}/Hz]. We then get

###### Evaluate

There is one particularly interesting thing to note about the derivation. The last term in (7.2) has units of voltage. Let us replace this with a voltage noise term *v*_{n}(*t*)vnt instead, so we find

*V*

_{s}≈

*A ω*

_{s}(

*t*−

*t*

_{n}) +

*v*

_{n}(

*t*).

As before, for this to be at a zero crossing we find

where we have assumed the terms *v*_{n}vn vary slowly compared with the main tone. We get

With this we see there is no way to distinguish the added voltage noise from the phase noise. We can look at the jitter phenomenon either as a phase noise or as an added voltage noise source. This is the root cause of the somewhat confusing units, as described earlier; we can view this spectrum as either a phase or a voltage for small phase deviations. Likewise, in modern simulators we can choose to calculate jitter from a phase noise integration or by looking at the voltage noise at the zero crossings. The two approaches should obviously agree. Note that this is, strictly speaking, only true when assumption 2 is valid. For large phase deviations we do not have correspondingly large voltage noise. Instead, the voltage noise has a natural limitation referred to as linewidth.

Finally, we note that when using the voltage noise domain approach, the voltage noise source transfers to jitter as

The denominator *Aω*_{s} = *dV*_{s}/*dt*Aωs=dVs/dt. We find

##### Summary

The jitter–phase noise relationship is a simple calculation of the phase noise power in a sideband divided by the fundamental tone cycle frequency. A simple sinusoidal noise source is helpful when explaining the jitter–phase noise relationship.

### 7.3 Phase-Locked Loops

Phase-locked loops (PLLs) and various varieties of them are in common use in the semiconductor industry. These systems are discussed in many books, including [2–5]. See, in particular, [4] for an interesting nonlinear analysis. They are the key element when it comes to clock and timing generation, and many topologies are used to meet the varying key specifications that are needed. How to simplify these systems to study them analytically is generally known, and we will just present the basic theory here. The first sections describes architectures, performance criteria and common PLL sub-blocks. We then describe the general transfer function for a second-order, type 2 PLL, while the following sections describe detailed calculations of stability and noise transfer for a PLL loop. Finally, a design example is provided.

#### Architectures

Traditionally phase-locked loops have been divided into integer-N and fractional-N PLLs. The integer-N PLL features a simple integer divider, while the fractional-N PLL has some kind of averaging technique implemented in the divider that makes it possible for the loop to lock to a continuous range of frequencies.

Exciting PLLs have been invented recently, such as subsampling PLLs that circumvent some of the shortcomings of the established topologies.

#### Performance Criteria

##### DC Specifications

*Power consumption*: A key DC specification is the power consumption. In modern life, battery powered devices are very popular and keeping the power consumption low for all the circuit components is critical for market success.

##### AC Specifications

We describe briefly the most common AC specifications for PLLs here.

*Loop bandwidth*: the closed loop bandwidth is a key to stability considerations. If it is too wide, the phase detector discrete sampling operation will cause problems. Depending on the cleanness of the on-chip VCO vs the reference oscillator, one might choose wide vs narrow bandwidths.

*Phase margin*: key to loop filter design and stability.

*Lock time*: the time it takes for a PLL to lock.

*Jitter*: the accuracy of the resulting clock is important for ADC applications, as will be discussed later in the chapter.

*Spur level*: spurs from the reference clock can show up in unexpected places.

#### PLL Sub-Blocks

A traditional PLL consists of four basic blocks: a phase detector, a VCO, a frequency divider, and a filter: see Figure 7.1. In this subsection we briefly describe them and derive some simple scaling rules.

Figure 7.1 Traditional phase-locked loop topology.

##### Phase Detector

The role of the phase detector is to amplify the phase difference between two input square waves, referred to as the reference clock and the, possibly divided down, oscillator clock. It can be implemented in many different ways, and we will not go into all the possibilities here. Instead, we will take a brief look at a phase frequency detector followed by a charge pump implementation, depicted in Figure 7.2. It is a very common workhorse in the industry.

Figure 7.2 A functional view of a phase detector implemented as a phase frequency detector with a charge pump.

The flip-flops are usually up or down edge sensitive. Depending on which edge comes first, the upper or lower current source is turned towards the output where it sources or sinks charge from the next block, which is the filter block consisting of a capacitor to ground, for simplicity. When the edge from the opposite source comes into the phase detector, the currents are turned off from the output. In this way the difference in phase between the reference and the divided down clock is translated into a current pulse. We can define the gain of this block as

The phase difference can go from +2*π*+2π to −2*π*−2π.

The time it will take to bring the PLL all the way from its start-up condition to phase lock is known as the pull-in time. Let us do an order of magnitude estimate of this time using estimation analysis.

###### Simplify

First we assume the output of the phase detector sits at ground and the VCO is tuned such that the correct output frequency occurs when the control voltage at the input, which is the same as the phase detector output, is at power supply VDD, typically 7–900 mV in small geometry CMOS. The charge pump needs to bring up the output node all the way from ground to VDD. We know from our earlier discussion, on comparator analysis in Chapter 3, that this scales like

The analysis is somewhat complicated by the fact the charge pump is only on for a limited time and it is possible the edge order will switch during the pull-in stage, depending on the overall dynamics. We will ignore such complications here.

###### Solve

This is now simply a matter of plugging in the numbers, and we find

In the last step we use the initial offset in frequency instead of voltage as a measure of how far one needs to go.

###### Verify

This is similar to other discussions, so here we have allowed ourselves a few shortcuts to arrive at a number very similar to what others have derived (see [2]).

###### Evaluate

It is clear that a small capacitance and a large current are helpful if a fast pull-in time is needed.

##### Voltage-Controlled Oscillator

The voltage-controlled oscillator will be discussed in much more detail in Section 7.4. Here we will just define the basic characteristics. The easiest way to change an oscillator’s frequency is to change the effective tank load; in almost all cases this means changing a capacitance, and in most modern CMOS technologies this is natural to transistors. There are often specially constructed varactor devices with this particular property such that their capacitance is changing with its bias voltage. We can now define the gain of a voltage-controlled oscillator as *K*_{VCO}KVCO and we find we have an output frequency

*ω*

_{out}=

*K*

_{VCO}

*V*

_{in}

with a given input voltage *V*_{in}Vin; note the unit of *K*_{VCO}KVCO is in angular frequency 2*πf*2πf [MHz/V]. The *K*_{VCO}KVCO is assumed to be constant for estimation calculations, but in a real circuitry it will vary with voltage.

For PLL analysis we are interested in phase and not in frequency, which can often be a confusing difference. Let us think of a sine wave

*V*= sin

*ωt*

The argument to the sinus function is a phase, but there is a frequency variable in the expression. Phase is defined as the integral of frequency. In our case in our sine wave we have a phase

In particular, for a time varying frequency this formula can be really helpful. We can now simply relate the input voltage to the oscillator to the output phase as

*θ*

_{out}(

*t*) = ∫

*ω*

_{out}

*dt*= ∫

*K*

_{VCO}

*V*

_{in}

*dt*

which in Laplace domain corresponds to a division by *s*s,

##### Frequency Divider

The frequency divider simply takes an input frequency and divides it by the desired factor *N*N. The corresponding change in phase is simply a division by *N*N. The gain is now

##### PLL Filter

We will discuss this block further in section “Fundamental Stability Discussion.” For now, we will simply describe it as a two-port system with transfer function *F*(*s*)Fs.

#### Basic PLL Equations

We can now pull all these block definitions together and derive the basic PLL equations. We will use the linearized transfer functions we derived in the previous section.

##### Simplify

We will consider a phase-locked loop as in Figure 7.3. It consists of an input reference signal, a phase detector (PD), a filter, a VCO and a divider circuit. The way to simplify such a system is to linearize all the blocks and assign a gain, or transfer function, to each one. These transfer functions for the various components are illustrated in the figure. Usually, the blocks are described in terms of Laplace transformations. In a typical application one is interested in the phase transfer in the loop, and all entities here refer to phase. The variable *s*s represents the modulation frequency around the nominal frequency. The linearization technique we describe here is known as the continuous time approximation where we ignore the fact that the phase detector–charge pump combination is actually a discrete time block. For this approximation to be valid, the loop filter bandwidth needs to be about 10× lower than the reference frequency.

Figure 7.3 Basic PLL topology with block gains.

##### Solve

We start by looking at the error signal,

We find explicitly,

We now find the transfer function *T*(*s*) = *v*_{o}(*s*)/*F*_{in}Ts=vos/Fin from input to the VCO output

##### Verify

This is a well-known calculation and can be found in most textbooks on PLLs.

##### Evaluate

Depending on the filter, we see we have at least a first-order characteristic equation in the denominator of equation (7.4).

#### Fundamental Stability Discussion

Stability of feedback systems is a well-studied subject, for example in [6, 7]. It comes up in many discussions, and a good understanding is very helpful in day-to-day engineering work. Here we will discuss it in the special context of PLL and second-order transfer functions. We will make some simplifying assumptions that are common in the subject and we hope the reader will be inspired to do explorations on his/her own. In the literature stability is usually discussed in terms phase margin and gain margin using Bode plots and open loop responses. This presentation uses the closed loop response to study stability. It is hoped that it will provide new insight and some variation to the more common open loop analysis. We leave it as an exercise for the reader to examine stability using open loop response.

We will use the transfer function we derived earlier and look at a couple of specific examples of the filter function, *F*(*s*)Fs, and see what it implies about the system’s stability.

We have for the closed loop gain

##### Simplify

For the filter function we will need a low-pass filter, and since the output of the charge pump is a current, the simplest low-pass filter is simply

We find then

##### Solve

This is a two-pole system and we can find the poles with a bit of rewrite:

From Appendix B we see this has the time solution

Clearly, while it does not have any increasing amplitude with time, the loop will oscillate. In most definitions of stability this situation is referred to as marginally stable, although in practice it is not acceptable. The oscillation frequency is called the natural frequency

With this definition we find for

The stability situation is not so good and we need to do something about that, but first let us look at the bandwidth. By replacing *s* → *jω*s→jω and looking at the magnitude of *T*(*jω*)Tjω, we have

We see there is a singularity at the natural frequency. Let us look beyond that (denominator changes sign) and find the 3 dB bandwidth.

In this case, the bandwidth is a tad higher than the natural frequency. As a side note, it is interesting that among the real PLLs one can buy in the market, there is often quite a bit of peaking around the natural frequency. We will see shortly that this kind of response is fairly straightforward to correct.

##### Evaluate

The expression for the bandwidth is dependent on the filter coefficients.

From a stability viewpoint, the simplification we did here in which we had a simple capacitor as integrator is simply not acceptable. In order to improve the situation we need to add a real part in the left-hand plane to the poles. We will investigate this in the next section.

##### Improved Stability

The suspicion is now that our loop filter is too trivial. We just have a simple integrator, a capacitor. Let us attempt a more complicated one.

###### Simplify

where *a* > 0a>0. For low frequencies we retain our integrator action, but for high frequencies we have added a zero resulting in a constant output.

###### Solve

Putting this into our original transfer function, we find

Let us solve for the roots

Since *a* > 0a>0 we see we have been successful in our quest of creating a pole in the left-hand plane. Furthermore, we see we can get rid of any oscillation by choosing

This particular choice is referred to as a critically damped system. Let us put this choice into the transfer function and solve for the time behavior

We find from an inverse Laplace transform the impulse response is

*T*(

*t*) =

*A te*

^{−ωnt}+

*Be*

^{−ωnt}.

There is a little bit of peaking and then the exponential roll-off.

This filter is simply a resistor in series with the capacitor. The input is a current and the output a voltage. We get

and

or

Finally, the bandwidth of the loop can now be estimated as

###### Evaluate

We have found a critically damped simple solution to our PLL model by making some simple assumptions and making them more complicated, to finally end up with a simple solution.

##### Summary

We have used estimation analysis to the full in this example and shown that we can derive some admittedly well-known results following the methodology.

A PLL’s stability can be improved by inserting a zero in the filter transfer function.

#### PLL Noise Transfer Analysis

Having derived the basic PLL parameters, we can now investigate noise transfer. The phase noise is particularly important when calculating jitter as we discussed in section “Phase Noise vs Jitter.” In this section we will discuss one noise calculation in detail and leave the rest as an exercise to the reader.

##### Noise Injected after the Filter

Noise injected after the loop filter can be estimated by simply adding in a noise signal as shown in Figure 7.4.

Figure 7.4 Basic PLL topology with noise injected after the filter.

###### Simplify

We simplify the situation by considering the various blocks around their normal bias point, so we can follow the situation described earlier.

###### Solve

Any noise injected after the filter will transfer as such:

Or,

We get at the VCO output

###### Evaluate

What does this mean? Let us go to various limits and observe the results, assuming *F*(*s*) = (1 + *as*)/(*Cs*)Fs=1+as/Cs. For high frequencies (large *s*) the second term in the denominator approaches a constant. This means the loop response to the high-frequency noise is simply a low-pass filter. For low frequencies, the second term in the denominator will dominate and the noise source *n*(*s*)ns will again be suppressed. In short, the loop acts as a band pass filter to the noise source.

##### Noise at the VCO Output Due to All Sources

Putting it all together, using the results from Exercise 7.1, we find at the VCO input the noise due to all noise sources in this simple model:

We can express these noise sources in terms of the PLL loop transfer function from equation (7.4).

These noise sources are uncorrelated and the resulting noise power can be written as

We see clearly the high pass function of the VCO transfer where most of the remaining blocks are low pass in nature.

A PLL transfer such as the VCO noise is high pass in nature, whereas the divider reference and phase detector are low pass in nature. Depending on the filter implementation, the filter noise response is often bandpass.

##### Example 7.1 Block design

Previously we discussed the basic equations determining the behavior of a PLL. We will here use them to define block specs for the individual blocks in the loop. This is an example of system design using the result of estimation analysis as a starting point. The fundamental parameters we derive can be put into a system simulator as a starting point for more detailed block-level specifications. Here, we will for brevity simply stop at the parameters provided by our simple model discussed in section “Basic PLL Equations.”

##### PLL Specifications

Specification | Value | Comment |
---|---|---|

Output frequency | 25 GHz | |

Input frequency | 2.5 GHz | |

Output phase noise | −130 dBc/Hz | @ 1 MHz offset from tone |

Bandwidth | 30 MHz |

##### PLL Block Definitions

From the specifications in Table 7.1 it is clear we need a divide ratio of 10. Let us look at the transfer function

We know *N* = 10N=10. It remains to define *K*_{VCO}, *C*KVCO,C, and *K*_{PD}KPD. For the charge pump we will choose a current of *I* = 1 mAI=1mA and a filter capacitance of *C* = 1 pFC=1pF. In a small geometry CMOS process we should have no difficulty with a 1 mA output current at 2.5 GHz. It is often better to use a higher charge pump gain than a high VCO gain due to the VCO sensitivity to the noise of the varactor. We can now look at the natural frequency and define the VCO gain.

Plugging in the numbers we find

This is a fairly reasonable number. We cover about 2.5% of the oscillator frequency and can make some adjustments for various center frequency shifts. We will use the *K*_{VCO}KVCO we derived here as a key specification for a VCO design later in this chapter. With a series resistor in the loop filter, it now remains to find this resistance, which we do by choosing a critically damped system. We have from equation (7.5)

With these parameters we find the key parameters illustrated in Table 7.2.

Parameter | Value | Units |
---|---|---|

NN |
1010 | |

K_{PD}KPD |
1/2π1/2π |
mA/rad |

K_{VCO}KVCO |
600600 | MHz/V |

n_{ref}nref |
00 | V |

n(s)ns |
00 | V |

n_{PD}nPD |
1.2 ⋅ 10^{−12}1.2⋅10−12 |
A/Hz |

n_{VCO}(s)nVCOs |
1/f1/f |
V/Hz |

n_{div}ndiv |
9 ⋅ 10^{−10}9⋅10−10 |
V/Hz |

CC |
11 | pF |

RR |
1010 | kohm |

A close-in phase noise response to the noise sources listed in Table 7.2 is shown in Figure 7.5.

Figure 7.5 Noise sources as a function of frequency offset in PLL. Note, no 1/f noise sources are included.

### 7.4 Voltage Controlled Oscillators

This section describes VCOs, and following the previous discussion of PLLs, we see that voltage noise at the input will translate to phase noise at the output. At the core of almost all high-performance integrated high speed oscillators is an LC resonator that determines the frequency of oscillation and often forms part of the feedback mechanism used to obtain sustained oscillations. In this section we describe how to solve for steady-state frequency, amplitude, phase noise, and finally a design example using estimation analysis. We base our discussion on references [6, 8–12].

#### Steady-State Frequency of Oscillation

The frequency of oscillation is naturally an important entity to understand when it comes to oscillators. We will calculate it with the help of estimation analysis.

##### Simplify

The analysis of a high-performance oscillator begins with an analysis of a damped LC resonator, such as the parallel resonator shown in Figure 7.6.

Figure 7.6 Simple model of VCO tank.

Since there are two reactive components, this is a second-order system, which can exhibit oscillatory behavior if the losses are low or if positive feedback is added. The values are fixed only at a given frequency. All the parameters vary with frequency, where the effective parallel resistance varies the most.

##### Solve

It is useful to find the system’s response to an external stimulus. We will solve this in two ways and show they are equivalent. First we will discuss a time domain solution, which we will use later. Then we will solve the same problem in the Laplace domain. First, let us look at the circuit in Figure 7.6 and analyze it using KCL:

*i*

_{C}+

*i*

_{R}+

*i*

_{L}= 0

We also know the inductor’s response to a change in current

We can this use in (7.6)

We now define

and we can rewrite

To solve these types of equation one can of course look up the solution in standard literature, but it is easier to work in the Laplace domain, which we will show shortly.

The general solution to this equation is

where *A*, *B*A,B are integration constants and can be determined from the initial conditions. The Laplace domain version of equation (7.7) becomes, by substituting *d*/*dt* → *s*d/dt→s